AD9166 datasheet(12/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 12 of 138

TIMING SPECIFICATIONS

Serial Port

DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,

DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC =3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3V, AMP_N5 = −5.0 V,

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. CS_x refers to CS_AMP and CS_DAC.

Table 9.

Parameter

Symbol

Test Comments/Conditions

Min

Typ

Max

Unit

WRITE OPERATION

See Figure 47

Maximum SCLK Clock Rate

fSCLK, 1/tSCLK

100

MHz

SCLK Clock High

tPWH

SCLK = 20 MHz

2.1

SCLK Clock Low

tPWL

SCLK = 20 MHz

4.3

SDIO to SCLK Setup Time

tDS

2.6

SCLK to SDIO Hold Time

tDH

3.5

1.5

CS_x to SCLK Setup Time

2.53

SCLK to CS_x Hold Time

6.7

READ OPERATION

See Figure 46

SCLK Clock Rate

fSCLK, 1/tSCLK

MHz

SCLK Clock High

tPWH

Not shown in Figure 46

SCLK Clock Low

tPWL

Not shown in Figure 46

SDIO to SCLK Setup Time

tDS

Not shown in Figure 46

SCLK to SDIO Hold Time

tDH

Not shown in Figure 46

CS_x to SCLK Setup Time

Not shown in Figure 46

SCLK to SDIO (or SDO) Data Valid Time

tDV

CS_x to SDIO (or SDO) Output Valid to High-Z

Not shown in Figure 46

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