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AD9166 Datasheet(PDF) 84 Page - Analog Devices |
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AD9166 Datasheet(HTML) 84 Page - Analog Devices |
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84 / 138 page ![]() AD9166 Data Sheet Rev. 0 | Page 84 of 138 Hex. Addr. Register Name Bit No. Bit Name Settings Description Reset Access 0 PLL_REF_CLK_PD PLL reference clock power- down. 0x0 R/W 0 Enable the PLL reference clock. 1 Power down the PLL reference clock. 0x088 SYSREF_CTRL0 [7:4] Reserved Reserved. 0x0 R 3 HYS_ON SYSREF± hysteresis enable. This bit enables the programmable hysteresis control for the SYSREF± receiver. 0x0 R/W 2 SYSREF_RISE Use SYSREF± rising edge. 0x0 R/W [1:0] HYS_CNTRL[9:8] Controls the amount of hysteresis in the SYSREF± receiver. Each of the 10 bits adds 10 mV of differential hysteresis to the receiver input. 0x0 R/W 0x089 SYSREF_CTRL1 [7:0] HYS_CNTRL[7:0] Controls the amount of hysteresis in the SYSREF± receiver. Each of the 10 bits adds 10 mV of differential hysteresis to the receiver input. 0x0 R/W 0x090 DLL_PD [7:5] Reserved Reserved. 0x0 R 4 DLL_FINE_DC_EN Fine delay line duty cycle correction enable. 0x1 R/W 3 DLL_FINE_XC_EN Fine delay line cross control enable. 0x1 R/W 2 DLL_COARSE_DC_EN Coarse delay line duty cycle correction enable. 0x1 R/W 1 DLL_COARSE_XC_EN Coarse delay line cross control enable. 0x1 R/W 0 DLL_CLK_PD Powers down DLL and digital clock generator. 0x1 R/W 0 Power up DLL controller. 1 Power down DLL controller. 0x091 DLL_CTRL 7 DLL_TRACK_ERR Track error behavior. 0x1 R/W 0 Continue on error. 1 Restart on error. 6 DLL_SEARCH_ERR Search error behavior. 0x1 R/W 0 Stop on error. 1 Retry on error. 5 DLL_SLOPE Desired slope. 0x1 R/W 0 Negative slope. 1 Positive slope. [4:3] DLL_SEARCH Search direction. 0x2 R/W 00 Search down from initial point only. 01 Search up from initial point only. 10 Search up and down from initial point. [2:1] DLL_MODE Controller mode. 0x0 R/W 00 Search then track. 01 Track only. 10 Search only. |
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