AD9166 datasheet(63/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 63 of 138

The clock receiver can compensate for phase imbalance of the

CLK+ and CLK− inputs (CLK_PHASE_TUNE register at

Address 0x07F). The register value is a signed binary, with the

MSB acting as the sign bit. Each additional step increase adds

20 fF of capacitance to either the CLK+ or the CLK− input. See

Table 41 for more details. Compensating for phase imbalance

improves the image rejection of the DAC.

Table 41. CLK± Phase Adjust Values

Bits[5:0]

Capacitance at

CLK+ (fF)

Capacitance at

CLK− (fF

000000

000001

1 × 20

000010

2 × 20

…

011111

31 × 20

100000

100001

1 × 20

100010

2 × 20

…

111111

31 × 20

The improvement in performance depends on the phase

balance of the external components as well as on the internal

clock path. Process variations may result in varying phase

balance across devices of the same population. Thus, if higher

levels of image rejection are desired, it may be beneficial to

calibrate each device independently, installed in the target

system. Performing this calibration has shown significant

improvements in some cases, in particular when less expensive

baluns are used.

Figure 91 shows how adjusting the clock phase, duty cycle, and

cross control can help compensate for phase and amplitude

imbalance at the CLK± pins.

PHASE 0,

CROSS 6

–20

–30

–40

–50

–60

–70

–80

–90

1000

2000

3000

4000

5000

6000

PHASE 28,

CROSS 10

fOUT (MHz)

Figure 91. Performance Improvement from Tuning the Clock Input

Delay Locked Loop (DLL)

The CLK± input goes to a high frequency DLL to ensure

reliable locking of the internal DAC sample clock to the input

clock. The DLL is configured and enabled as part of the

recommended start-up sequence. The DLL control registers are

located at Register 0x090 through Register 0x09B. The DLL

settings are determined during product characterization and are

given in the recommended start-up sequence (see the Start-Up

Sequence section). It is not normally necessary to change these

values, and the product characterization data is valid only with the

recommended settings.

SHUFFLE MODE

The spurious performance of the AD9166 can be improved with

a feature called shuffle mode. Shuffle mode uses proprietary

technology to spread the energy of spurious signals across the

DAC output as random noise. Shuffle mode is enabled by

programming Register 0x151, Bit 2 = 0b1. Because shuffle mode

is implemented using the MSB current sources of the DAC, it is

most effective when the DAC is operated with a small amount

of digital backoff relative to 0 dBFS.

The amount of noise rise at the output of the DAC core caused

by shuffle mode is directly related to the power in the affected

spurious signals. Because the AD9166 has a wideband buffer

amplifier at the output of the DAC core, the increase in noise

spectral density is not apparent with or without shuffle.

Shuffle mode improves the spurious performance related to

clock and foldback spurs, but does not affect real harmonics

generated at the DAC output.

VOLTAGE REFERENCE AND FULL-SCALE CURRENT

(FSC)

The full-scale current at the DAC output, IOUTFS, controls the

maximum output current swing out of the DAC and into the

input of the buffer amplifier. When adjusting IOUTFS, the input

common-mode current of the buffer amplifier, ICM, must be

adjusted to match the IOUTFS value of the DAC.

ICM is set using the digital control bits (AMP_ICM, Amplifier

value that matches IOUTFS. For more details, see the Adjusting ICM

to Match IOUTFS section.

IOUTFS is set through a combination of digital control bits and the

reference current, ISET, as shown in Figure 92.

CURRENT

SCALING

ANA_FULL_SCALE_CURRENT [9:0]

AD9166

DAC

IOUTFS

9.6kΩ

1µF

VREF

ISET

VSS

ISET

VBG

1.2V

–

DAC_N1P2_AN

Figure 92. Voltage Reference Circuit

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