AD9166 datasheet(96/138 Pages) AD

96 / 138 page

AD9166

Data Sheet

Rev. 0 | Page 96 of 138

Hex.

Addr.

Bit

No.

Bit Name

Settings

Description

Reset

Access

0x2BF

TERM_OFFSET_4

[7:4] Reserved

Reserved.

0x0

[3:0] TERM_OFFSET_4

Add or subtract from the

termination calibration value

of Physical Lane 4. 4-bit signed

magnitude value that adds to

or subtracts from the

termination value. Bit 3 is the

sign bit, and Bits[2:0] are the

magnitude bits.

0x0

R/W

0x2C0

TERM_OFFSET_5

[7:4] Reserved

Reserved.

0x0

[3:0] TERM_OFFSET_5

Add or subtract from the

termination calibration value

of Physical Lane 5. 4-bit signed

magnitude value that adds to

or subtracts from the

termination value. Bit 3 is the

sign bit, and Bits[2:0] are the

magnitude bits.

0x0

R/W

0x2C1

TERM_OFFSET_6

[7:4] Reserved

Reserved.

0x0

[3:0] TERM_OFFSET_6

Add or subtract from the

termination calibration value

of Physical Lane 6. 4-bit signed

magnitude value that adds to

or subtracts from the

termination value. Bit 3 is the

sign bit, and Bits[2:0] are the

magnitude bits.

0x0

R/W

0x2C2

TERM_OFFSET_7

[7:4] Reserved

Reserved.

0x0

[3:0] TERM_OFFSET_7

Add or subtract from the

termination calibration value

of Physical Lane 7. 4-bit signed

magnitude value that adds to

or subtracts from the

termination value. Bit 3 is the

sign bit, and Bits[2:0] are the

magnitude bits.

0x0

R/W

0x300

GENERAL_JRX_CTRL_0

Reserved

Reserved.

0x0

CHECKSUM_MODE

JESD204B link parameter

checksum calculation method.

0x0

R/W

0 Checksum is sum of fields.

1 Checksum is sum of octets.

[5:1] Reserved

Reserved.

0x0

LINK_EN

This bit brings up the

JESD204B receiver when all

link parameters are

programmed and all clocks

are ready.

0x0

R/W

0x302

DYN_LINK_LATENCY_0

[7:5] Reserved

Reserved.

0x0

[4:0] DYN_LINK_LATENCY_0

Measurement of the JESD204B

link delay (in PCLK units).

Link 0 dynamic link latency.

Latency between current

deframer LMFC and the global

LMFC.

0x0

0x304

LMFC_DELAY_0

[7:5] Reserved

Reserved.

0x0

[4:0] LMFC_DELAY_0

Fixed part of the JESD204B

link delay (in PCLK units).

Delay in frame clock cycles for

global LMFC for Link 0.

0x0

R/W

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