AD9166 datasheet(28/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 28 of 138

SERIAL PORT OPTIONS

The serial port can support both MSB first and LSB first data

formats. This functionality is controlled by the LSB first bit

(Register 0x000, Bit 6 and Bit 1). The default is MSB first (LSB

bit = 0).

When the LSB first bits = 0 (MSB first), the instruction and data

bits must be written from MSB to LSB. Read/write (R/W) is

followed by the instruction word, A[14:0], and D[7:0], the data-

word. When the LSB first bits = 1 (LSB first), the opposite is

true. A[0:14] is followed by R/W, which is subsequently

followed by D[0:7].

The serial port supports a 3-wire or 4-wire interface. When the

SDO active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire

interface with a separate input pin (SDIO) and output pin (SDO) is

used. When the SDO active bits = 0, the SDO pin is unused and

the SDIO pin is used for both the input and the output.

Multibyte Data Transfers

Multibyte data transfers can be performed by holding CS_AMP

or CS_DAC low for multiple data transfer cycles (eight SCLK

cycles) after the first data transfer word following the instruction

cycle. The first eight SCLK cycles following the instruction cycle

read from or write to the register provided in the instruction

cycle. For each additional eight SCLK cycles, the address is

either incremented or decremented and the read/write occurs

on the new register. The direction of the address is set using

ADDRINC or ADDRINC_M (Register 0x000, Bit 5 and Bit 2).

When ADDRINC or ADDRINC_M is 1, the multicycle

addresses are incremented. When ADDRINC or ADDRINC_M

is 0, the addresses are decremented. A new write cycle can

always be initiated by bringing CS_x high and then low again.

To prevent confusion and to ensure consistency between

devices, the chip tests the first nibble following the address

phase, ignoring the second nibble. This test is completed

independently from the LSB first bits and ensures that there are

extra clock cycles following the soft reset bits (Register 0x000,

Bit 0 and Bit 7). This test of the first nibble only applies when

writing to Register 0x000.

R/W A14 A13

A2 A1 A0 D7N D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

CS_x

Figure 44. Serial Register Interface Timing, MSB First, Register 0x000, Bit 5

and Bit 2 = 0

A0 A1 A2

A12 A13 A14

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

R/W

CS_x

Figure 45. Serial Register Interface Timing, LSB First, Register 0x000, Bit 5 and

Bit 2 = 1

SCLK

SDIO

CS_x

DATA BITn– 1

DATA BIT n

tDV

Figure 46. Timing Diagram for Serial Port Register Read

SCLK

SDIO

CS_x

INSTRUCTION BIT 14

INSTRUCTION BIT 0

INSTRUCTION BIT 15

tDS

tDH

tPWH

tPWL

Figure 47. Timing Diagram for Serial Port Register Write

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