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AD9166 Datasheet(PDF) 68 Page - Analog Devices |
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AD9166 Datasheet(HTML) 68 Page - Analog Devices |
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68 / 138 page  AD9166 Data Sheet Rev. 0 | Page 68 of 138 Table 43. Configure JESD204B Start-Up Sequence Register Value Description R/W 0x300 0x00 Ensure the SERDES links are disabled before configuring them. W 0x480 0x38 Enable SERDES error counters. W 0x481 0x38 Enable SERDES error counters. W 0x482 0x38 Enable SERDES error counters. W 0x483 0x38 Enable SERDES error counters. W 0x484 0x38 Enable SERDES error counters. W 0x485 0x38 Enable SERDES error counters. W 0x486 0x38 Enable SERDES error counters. W 0x487 0x38 Enable SERDES error counters. W 0x110 Configure number of lanes (Bits[7:4]) and interpolation rate (Bits[3:0]). W 0x111 Configure the datapath options for Bit 7 (INVSINC_EN), Bit 6 (NCO_EN), Bit 4 (FILT_BW), Bit 2 (MODULUS_EN), Bit 1 (SEL_SIDEBAND), and Bit 0 (FIR85_FILT_EN). See the Register Summary section for details on the options. Set the reserved bits (Bit 5 and Bit 3) to 0b0. W 0x230 Configure the CDR block according to Table 19 for both half rate enable and the divider. W 0x289, Bits[1:0] Set up the SERDES PLL divider based on the conditions shown in Table 18. W 0x084, Bits[5:4] Set up the PLL reference clock rate based on the conditions shown in Table 18. W 0x200 0x00 Enable the JESD204B block (disable master SERDES power-down). W 0x475 0x09 Soft reset the JESD204B quad-byte deframer. W 0x453, Bit 7 0b1 Optional. Enable scrambling on SERDES lanes. W 0x458, Bits[7:5] Set the subclass type: 0b000 = Subclass 0, 0b001 = Subclass 1. W 0x459, Bits[7:5] 0b1 Set the JESD204x version to JESD204B. W 0x45D Program the calculated checksum value for Lane 0 from values in Register 0x450 to Register 0x45C. W 0x475 0x01 Bring the JESD204B quad-byte deframer out of reset. W 0x201, Bits[7:0] Set any bits to 1 to power down the appropriate physical lane. W 0x2A7 0x01 Optional. Calibrate SERDES PHY Termination Block 1 (PHY 0, PHY 1, PHY 6, PHY 7). W 0x2AE 0x01 Optional. Calibrate SERDES PHY Termination Block 2 (PHY 2, PHY 3, PHY 4, PHY 5). W 0x29E 0x1F Override defaults in the SERDES PLL settings (private). W 0x280 0x03 Enable the SERDES PLL. W 0x281, Bit 0 0b1 Read back Register 0x281 until Bit 0 = 1 to indicate the SERDES PLL is locked. R Prior to enabling the link, be sure that the JESD204B transmitter is enabled and ready to begin link synchronization. 0x206 0x00 Reset the CDR to realign the sampling clock with the incoming data. W 0x206 0x01 Bring the CDR out of reset. W 0x300 0x01 Enable the JESD204B receiver to begin link synchronization. When SYNCOUT± is asserted, the JESD204B transmitter begins CGS by sending /K/ characters. W 0x470 0xFF Read the CGS status for all lanes. R 0x471 0xFF Read the frame sync status for all lanes. R 0x472 0xFF Read the good checksum status for all lanes. R 0x473 0xFF Read the initial lane sync status for all lanes. R 0x024 0x1F Clear the datapath interrupts. W 0x4BA 0xFF Clear the SERDES interrupts. W 0x4BB 0x01 Clear the SERDES interrupt. W 0x020 0x0F Optional. Enable the interrupts. W 0x4B8 0xFF Optional. Enable JESD204B interrupts. W 0x4B9 0x01 Optional. Enable JESD204B interrupts. W |
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