AD9166 datasheet(41/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 41 of 138

Link Delay Setup Example, Without Known Delay

If the system delays are not known, the AD9166 can read back

the link latency between LMFCRX for each link and the

SYSREF± aligned LMFC. This information is then used to

calculate LMFCVar and LMFCDel. Figure 62 shows how

DYN_LINK_LATENCY_0 (Register 0x302) provides a

readback showing the delay (in PCLK cycles) between the

LMFCRX and the transition from the ILAS to the first data

sample. By repeatedly power cycling and taking this measurement,

the minimum and maximum delays across power cycles can be

determined to calculate LMFCVar and LMFCDel.

In Figure 62, the AD9166 is configured as described in the Sync

Procedure section. Because the purpose of this exercise is to

determine LMFCDel and LMFCVar, the LMFCDel value is

programmed to 0 and the DYN_LINK_LATENCY_0 value is

read from Register 0x302. For Link A, Link B, and Link C, the

system containing the AD9166 (including the transmitter) is

power cycled and configured 20 times.

The variation in the link latency over the 20 runs is shown in

Figure 62, described as follows:



Link A gives readbacks of 6, 7, 0, and 1. Note that the set of

recorded delay values rolls over the edge of a multiframe at

the boundary of K/PCLK factor = 8. Add the number of

PCLK cycles per multiframe = 8 to the readback values of 0

and 1 because they rolled over the edge of the multiframe.

Delay values range from 6 to 9.



Link B gives delay values from 5 to 7.



Link C gives delay values from 4 to 7.

The example shown in Figure 62 is demonstrated in the

following steps. Note that this example is in Subclass 1 to

achieve deterministic latency, which has a PCLK factor (frame

rate ÷ PCLK rate) of 4 and uses K = 32. Therefore, PCLK cycles

per multiframe = 8.

Calculate the minimum of all delay measurements across

all power cycles, links, and devices as follows:

MinDelay = min(all Delay values) = 4

Calculate the maximum of all delay measurements across

all power cycles, links, and devices as follows:

MaxDelay = max(all Delay values) = 9

Calculate the total delay variation (with guard band) across

all power cycles, links, and devices as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (9 + 1) − (4 − 1) = 10 − 3 = 7 PCLK cycles

Calculate the minimum delay in PCLK cycles (with guard

band) across all power cycles, links, and devices as follows:

LMFCDel

= (MinDelay − 1) % (K/PCLK Factor)

= (4 − 1) % 32/4

= 3 % 8 = 3 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the system.

Write LMFCVar to Register 0x306 for all devices in the system.

0123

45670123

4567

DYN_LINK_LATENCY_0 COUNT

ALIGNED DATA (LINK A)

DETERMINISTICALLY

DELAYED DATA

LMFCRX

ALIGNED DATA (LINK B)

ALIGNED DATA (LINK C)

FRAME CLOCK

LMFC

PCLK

DATA

ILAS

DATA

ILAS

DATA

ILAS

DATA

ILAS

LMFC_DELAY_0 = 6

(FRAME CLOCK CYCLES)

LMFC_VAR_0 = 7

(PCLK CYCLES)

Figure 62. Multilink Synchronization Settings, Derived Method Example

ILAS

DATA

SYSREF±

ALIGNED DATA

LMFCRX

DYN_LINK_LATENCY_0

Figure 63. DYN_LINK_LATENCY_0

AD9166 Datasheet(PDF) 41 Page - Analog Devices

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