AD9166 datasheet(86/138 Pages) AD

86 / 138 page

AD9166

Data Sheet

Rev. 0 | Page 86 of 138

Hex.

Addr.

Bit

No.

Bit Name

Settings

Description

Reset

Access

[3:0] INTERP_MODE

Interpolation mode. For

proper operation of the

JESD204B data link, this signal

must only be programmed

while the QBD is held in soft

reset (Register 0x475, Bit 3),

and must not be changed

during normal operation.

0x1

R/W

0000 1× (bypass).

0001 2×.

0010 3×.

0011 4×.

0100 6×.

0101 8×.

0110 12×.

0111 16×.

1000 24×.

0x111

DATAPATH_CFG

INVSINC_EN

Inverse sinc filter enable.

0x0

R/W

0 Disable inverse sinc filter.

1 Enable inverse sinc filter.

NCO_EN

Modulation enable.

0x0

R/W

0 Disable NCO.

1Enable NCO.

Reserved

Reserved.

0x0

FILT_BW

Datapath filter bandwidth.

0x0

R/W

0 Filter bandwidth is 80%.

1 Filter bandwidth is 90%.

Reserved

Reserved.

0x0

MODULUS_EN

Modulus DDS enable.

0x0

R/W

0 Disable modulus DDS.

1 Enable modulus DDS.

SEL_SIDEBAND

Selects upper or lower

sideband from modulation

result.

0x0

R/W

0 Use upper sideband.

1 Use lower sideband = spectral

flip.

FIR85_FILT_EN

FIR85 filter enable.

0x0

R/W

0x113

FTW_UPDATE

Reserved

Reserved.

0x0

[6:4] FTW_REQ_MODE

Frequency tuning word (FTW)

automatic update mode.

0x0

R/W

000 No automatic requests are

generated when the FTW

registers are written.

001 Automatically generate

FTW_LOAD_REQ after FTW0 is

written.

010 Automatically generate

FTW_LOAD_REQ after FTW1 is

written.

011 Automatically generate

FTW_LOAD_REQ after FTW2 is

written.

100 Automatically generate

FTW_LOAD_REQ after FTW3 is

written.

101 Automatically generate

FTW_LOAD_REQ after FTW4 is

written.

AD9166 Datasheet(PDF) 86 Page - Analog Devices

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