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AD9166 Datasheet(PDF) 15 Page - Analog Devices |
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AD9166 Datasheet(HTML) 15 Page - Analog Devices |
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15 / 138 page  Data Sheet AD9166 Rev. 0 | Page 15 of 138 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A B C D E F G H J K L M N P R T U V DNC = DO NOT CONNECT. LEAVE THESE PINS FLOATING. 3.3V ANALOG SUPPLY, BUFFER OUTPUT –5V ANALOG SUPPLY, BUFFER REFERENCE 5V ANALOG SUPPLY, BUFFER INPUT 2.5V ANALOG SUPPLY, DAC OUTPUT –1.2V ANALOG SUPPLY, DAC OUTPUT 1.2V ANALOG SUPPLY, DAC CLOCK 1.2V ANALOG SUPPLY, DAC MIXED-SIGNAL CMOS I/O GND REFERENCE DNC 1.2V SERDES SUPPLY 1.2V DIGITAL SUPPLY I/O PINS SUPPLY (1.8V TO 3.3V) 3.3V SYNCOUT+/SYNCOUT– SUPPLY SERDES LANE x SYSTEM REFERENCE POSITIVE AND NEGATIVE RF SIGNALS BYPASS NODE REFERENCE NODE 1 2 3 45 6 7 89 10 11 12 13 14 15 16 17 18 TOP VIEW (Not to Scale) GND GND GND GND GND GND GND GND GND GND GND GND RFOUT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMP_ VBG CS_AMP GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DAC_ 1P2_ SER DAC_ 1P2_ SER DAC_ 1P2_ SER GND GND SERPLL_ LDO_ BYPASS GND DAC_ 1P2_ SER DAC_ 1P2_ SER DAC_ 1P2_ SER GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMP_ 3P3 AMP_ 3P3 AMP_ N5 AMP_ N5 AMP_ 3P3_ OUT AMP_ 3P3_ OUT GND GND CLK+ GND AMP_N5 AMP_N5 AMP_N5 VDD_IO GND CLK– GND GND AMP_ 5V_ IN AMP_ 5V_ IN AMP_ 5V_ IN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SYS REF+ SYS REF– GND GND DNC GND GND GND GND GND GND DAC_ VBG NEG GND GND GND GND GND GND GND GND DNC DAC_ 2P5_AN GND GND GND GND GND SDIO SDO SCLK GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DNC GND GND GND GND GND SERDIN 7+ SERDIN 7– SERDIN 0+ SERDIN 0– SERDIN 1+ SERDIN 1– SERDIN 6– SERDIN 5+ SERDIN 5– SERDIN 4+ SERDIN 4– SERDIN 3– SERDIN 3+ SERDIN 2– SERDIN 2+ SERDIN 6+ GND GND GND GND DAC_ 1P2_ SER IRQ GND GND GND GND GND GND DAC_ 1P2_ SER GND GND GND GND VDD_IO DAC_ 1P2_ SER GND DAC_ 1P2_ SER RESET TX_ ENABLE DAC_ 1P2_ SER DAC_ 1P2_ SER VDD_IO CS_DAC GND DAC_ 1P2_ SER GND GND GND GND GND GND DAC_ 1P2_ DIG DAC_ 1P2_ DIG DAC_ 1P2_ DIG DAC_ 1P2_ SER GND DAC_ 1P2_ DIG DAC_ 1P2_ DIG DAC_ 1P2_ DIG DAC_ 1P2_ DIG DAC_ 1P2_ DIG DAC_ 1P2_ DIG DAC_ 1P2_ SER GND GND GND GND DAC_ 3P3_ SYNC DAC_ 3P3_ SYNC DNC GND GND DAC_ 1P2_ SER DAC_ 1P2_ SERDES DAC_ 1P2_ SER GND SYNC OUT– SYNC OUT+ DAC_ 1P2_ SER DAC_ 1P2_ SER GND GND GND GND GND DAC_ N1P2 _AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 2P5_AN DAC_ 1P2_AN DAC_ 1P2_ CLK DAC_ 1P2_ CLK DAC_ 1P2_ CLK DAC_ 1P2_ CLK DAC_ 1P2_ CLK DAC_ 1P2_ CLK DAC_ 1P2_ CLK DAC_ 1P2_AN DAC_ 2P5_AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ N1P2 _AN DAC_ 1P2_ CLK DAC_ 1P2_ CLK GND GND ISET VREF GND GND AMP_ 1P8_ BYPASS AMP_ 1P8_ BYPASS GND GND Figure 3. Pin Configuration Table 13. Pin Function Descriptions Pin No. Mnemonic Description A1 to A8, A10 to A18, B1 to B12, B15 to B18, C1, C2, C8 to C10, C12, C15, C18, D1, D2, D9, D10, D18, E2, E18, F2 to F4, F10, F11, F17, F18, G1 to G9, G17, G18, H2 to H6, H8 to H10, H14 to H18, J2 to J7, J10, J11, J15 to J18, K1 to K12, K14 to K18, L2, L3, L6 to L14, L16, L17, M2, M3, M9, M14, M16, M17, N1 to N3, N5, N16 to N18, P2 to P4, P9, P11, P16, P17, R2 to R4, R8, R9, R11, R16, R17, T1 to T18, U1 to U18, V1 to V3, V6, V9, V10, V13, V16 to V18 GND Ground. A9 RFOUT Device RF Output. Internally matched to a 50 Ω single- ended load impedance. |
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