AD9166 datasheet(62/138 Pages) AD

62 / 138 page

AD9166

Data Sheet

Rev. 0 | Page 62 of 138

2× NRZ Mode

The AD9166 has an additional mode that allows doubling the

DAC sample rate. The 2× NRZ mode is implemented using the

FIR85 2× interpolation filter, which provides new samples to

the DAC core on both rising and falling edges of the device

clock. As a result, the analog bandwidth in 2× NRZ mode also

doubles in comparison to NRZ mode, as illustrated in Figure 88.

Because the DAC sample rate (fDAC) is now twice the device

clock (fCLK), the energy in the image frequency at fCLK – fOUT

appears at 2 × fCLK – fOUT. Assuming the differential device clock

has perfect phase and amplitude balance, the image at fCLK – fOUT

can be eliminated altogether. Phase imbalance can be compensated

in the device clock receiver of the AD9166. See the Clock Input

section for more details.

Because the FIR85 interpolator is sampling at a higher rate, it

also consumes more power when compared to a similar NRZ

mode, RZ mode, or mix mode.

–36

–33

–30

–27

–24

–21

–18

–15

–12

–9

–6

–3

00.4

fCLK

0.8

fCLK

1.2

fCLK

1.6

fCLK

2.0

fCLK

FREQUENCY (Hz)

NRZ MODE

2× NRZ MODE

MIX MODE

RZ MODE

Figure 88. Sinc Roll-Off for 2× NRZ, NRZ, RZ, and Mix Mode Operation

CLOCK INPUT

The AD9166 contains a low jitter, differential clock receiver that

is capable of interfacing directly to a differential or single-ended

clock source. Because the input is self biased with a nominal

impedance of 90 Ω, it is recommended that the clock source be

ac-coupled to the CLK± input pins. The nominal differential input

is 1 V p-p, but the clock receiver can operate with a span that

ranges from 250 mV p-p to 2.0 V p-p.

Higher clock input level results in improved phase noise (phase

jitter) performance, because the higher swing results in a higher

slew rate (faster rise time).

CLK+

TO DAC

AND DLL

CLK–

1.25V

5kΩ

40kΩ

16µA

DUTY CYCLE

RESTORER

CROSS

CONTROL

Figure 89. Clock Input

The quality of the clock source, as well as its interface to the

AD9166 clock input, directly impacts ac performance. Select the

phase noise and spur characteristics of the clock source to meet

the target application requirements. Phase noise and spurs at a

given frequency offset on the clock source are directly translated

to the output signal. Specifically, it can be shown that the phase

noise characteristics of a reconstructed output sine wave are

related to the clock source by 20 × log10 (fOUT/fDAC) when the

internal device clock path contribution is negligible.

Figure 90 shows a clock source based on the ADF4372 low phase

noise/jitter PLL. The ADF4372 can provide output frequencies

from 62.5 MHz up to 16,000 MHz using the RF16x port and up

to 8,000 MHz using the RF8x or RFAUX8x ports.

Adjusting Clock Duty-Cycle and Differential Phase

Imbalance

The clock control registers exist at Register 0x082 through

enable duty cycle correction (Bit 7), enable duty cycle offset

control (Bit 6), and set the duty cycle offset (Bits[4:0]). The duty

cycle offset word is a signed magnitude word, with Bit 4 as the

sign bit (1 is negative) and Bits[3:0] as the magnitude. The duty

cycle adjusts across a range of approximately ±3%. Recommended

settings for this register are listed in the Start-Up Sequence section.

VCO

PLL

ADF4372

fREF

2GHz TO 6GHz

0dBm

100pF

7.4nH

VOUT

7.4nH

100pF

AD9166

CLK+

CLK–

OUTPUT

STAGE

Figure 90. Possible Signal Chain for CLK± Input

AD9166 Datasheet(PDF) 62 Page - Analog Devices

AD9166 Datasheet(HTML) 62 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL