AD9166 datasheet(85/138 Pages) AD

85 / 138 page

Data Sheet

AD9166

Rev. 0 | Page 85 of 138

Hex.

Addr.

Bit

No.

Bit Name

Settings

Description

Reset

Access

DLL_ENABLE

Controller enable.

0x0

R/W

0 Disable DLL controller: use

static SPI settings.

1 Enable DLL controller: use

controller with feedback loop.

0x092

DLL_STATUS

[7:3] Reserved

Reserved.

0x0

DLL_FAIL

The device clock DLL failed to

lock.

0x0

DLL_LOST

The device clock DLL has lost

lock.

0x0

R/W

DLL_LOCKED

The device clock DLL has

achieved lock.

0x0

0x093

DLL_GB

[7:4] Reserved

Reserved.

0x0

[3:0] DLL_GUARD

Search guard band.

0x0

R/W

0x094

DLL_COARSE

[7:6] Reserved

Reserved.

0x0

[5:0] DLL_COARSE

Coarse delay line setpoint.

0x0

R/W

0x095

DLL_FINE

[7:0] DLL_FINE

Fine delay line setpoint.

0x80

R/W

0x096

DLL_PHASE

[7:5] Reserved

Reserved.

0x0

[4:0] DLL_PHS

Desired phase.

0x8

R/W

0 Minimum allowed phase.

16 Maximum allowed phase.

0x097

DLL_BW

[7:5] Reserved

Reserved.

0x0

[4:2] DLL_FILT_BW

Phase measurement filter

bandwidth.

0x0

R/W

[1:0] DLL_WEIGHT

Tracking speed.

0x0

R/W

0x098

DLL_READ

[7:1] Reserved

Reserved.

0x0

DLL_READ

Read request: 0 to 1 transition

updates the coarse, fine, and

phase readback values.

0x0

R/W

0x099

DLL_COARSE_RB

[7:6] Reserved

Reserved.

0x0

[5:0] DLL_COARSE_RB

Coarse delay line readback.

0x0

0x09A

DLL_FINE_RB

[7:0] DLL_FINE_RB

Fine delay line readback.

0x0

0x09B

DLL_PHASE_RB

[7:5] Reserved

Reserved.

0x0

[4:0] DLL_PHS_RB

Phase readback.

0x0

0x09D

DIG_CLK_INVERT

[7:3] Reserved

Reserved.

0x0

INV_DIG_CLK

Invert digital clock from DLL.

0x0

R/W

0 Normal polarity.

1 Inverted polarity.

DIG_CLK_DC_EN

Digital clock duty cycle

correction enable.

0x1

R/W

DIG_CLK_XC_EN

Digital clock cross control

enable.

0x1

R/W

0x0A0

DLL_CLK_DEBUG

DLL_TEST_EN

DLL clock output test enable.

0x0

R/W

[6:2] Reserved

Reserved.

0x0

[1:0] DLL_TEST_DIV

DLL clock output divide.

0x0

R/W

0x110

INTERP_MODE

[7:4] JESD_LANES

Number of JESD204B lanes.

For proper operation of the

JESD204B data link, this signal

must only be programmed

while the QBD is held in soft

reset (Register 0x475, Bit 3),

and must not be changed

during normal operation.

0x8

R/W

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