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AD9166 Datasheet(PDF) 7 Page - Analog Devices

Part # AD9166
Description  DC to 9 GHz Vector Signal Generator
PDF  138 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9166 Datasheet(HTML) 7 Page - Analog Devices

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Data Sheet
AD9166
Rev. 0 | Page 7 of 138
DEVICE INPUT CLOCK RATE AND DAC UPDATE RATE SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperature and voltage conditions shown in Table 3, where DAC_1P2_x includes DAC_1P2_AN,
DAC_1P2_CLK, DAC_1P2_DIG, and DAC_1P2_SER. Any device clock speed over 5.1 GHz requires a maximum junction temperature not
exceeding 105°C to avoid damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.
Table 3.
Parameter
Test Conditions/Comments1
Min
Typ
Max
Unit
MAXIMUM INPUT CLOCK RATE (fCLK)
DAC_1P2_x = 1.2 V ± 5%
TJ_DAC_MAX = 25°C
6.0
GHz
TJ_DAC_MAX = 85°C
5.6
GHz
TJ_DAC_MAX = 105°C
5.4
GHz
DAC_1P2_x = 1.2 V ± 2%
TJ_DAC_MAX = 25°C
6.1
GHz
TJ_DAC_MAX = 85°C
5.8
GHz
TJ_DAC_MAX = 105°C
5.6
GHz
DAC_1P2_x = 1.3 V ± 2%
TJ_DAC_MAX = 25°C
6.4
GHz
TJ_DAC_MAX = 85°C
6.2
GHz
T_DAC_MAX = 105°C
6.0
GHz
DAC UPDATE RATE (fDAC)
Minimum
1.5
GSPS
Maximum
DAC_1P2_x = 1.3 V ± 2%
6
6.4
GSPS
DAC_1P2_x = 1.3 V ± 2%, FIR85 (2× NRZ) enabled
12
12.8
GSPS
Adjusted2
DAC_1P2_x = 1.3 V ± 2%
6
6.4
GSPS
1 TJ_DAC_MAX is the maximum junction temperature measured using the DAC temperature sensor.
2 The adjusted DAC update rate is calculated as follows: when FIR85 is disabled, fDAC is divided by the minimum required interpolation factor. For the AD9166, the
minimum interpolation factor is 1. Therefore, with fDAC = 6.0 GSPS, fDAC adjusted = 6.0 GSPS. When FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 ×
fCLK, and the minimum interpolation is 2× (interpolation value). Thus, for the AD9166, with FIR85 enabled and fCLK = 6 GHz, fDAC = 12.0 GSPS, minimum interpolation = 2×, and the
adjusted DAC update rate = 6.0 GSPS.



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