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PM5356 Datasheet(PDF) 28 Page - PMC-Sierra, Inc |
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PM5356 Datasheet(HTML) 28 Page - PMC-Sierra, Inc |
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28 / 307 page ![]() RELEASED S/UNI-622-MAX PMC-Sierra, Inc. PM5356 S/UNI-622-MAX DATASHEET PMC-1980589 ISSUE 6 SATURN USER NETWORK INTERFACE (622-MAX) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18 Pin Name Type Pin No. Function RRCLK+ RRCLK- Differential PECL Input U1 U2 When clock recovery is bypassed (RBYP set high), RRCLK+/- is nominally a 622.08 MHz 50% duty cycle clock and provides timing for the S/UNI-622-MAX receive functions. In this case, RXD+/- is sampled on the rising edge of RRCLK+/-. RRCLK+/- is ignored when RBYP is set low. Please refer to the Operation section for a discussion of PECL interfacing issues. SD PECL Input R2 The receive signal detect PECL input (SD) indicates the presence of valid receive signal power from the Optical Physical Medium Dependent Device. A PECL logic high indicates the presence of valid data. A PECL logic low indicates a loss of signal. Please refer to the Operation section for a discussion of PECL interfacing issues TXD+ TXD- Differential PECL Output L2 L1 The transmit differential data PECL outputs (TXD+/-) contain the 622.08 Mbit/s transmit stream. The TXD+/- outputs are driven using the synthesized clock from the CSU-622. Please refer to the Operation section for a discussion of PECL interfacing issues. |
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