PM5356 datasheet(72/307 Pages) PMC

72 / 307 page

RELEASED

S/UNI-622-MAX

PMC-Sierra, Inc.

PM5356

S/UNI-622-MAX

DATASHEET

PMC-1980589

ISSUE 6

SATURN USER NETWORK INTERFACE (622-MAX)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

10.12.2

Transmit ATM Interface

The ATM Transmit FIFO (TXCP) provides FIFO management and the S/UNI-622-

MAX transmit cell interface. The transmit FIFO contains four cells. The FIFO

depth may be programmed to four, three, two, or one cells. The FIFO provides

the cell rate decoupling function between the transmission system physical layer

and the ATM layer.

In general, the management functions include emptying cells from the transmit

FIFO, indicating when the transmit FIFO is full, maintaining the transmit FIFO

read and write pointers and detecting a FIFO overrun condition.

The interface can be configured either as a 16-bit UTOPIA Level 2 interface, or

as an 8-bit UTOPIA Level 3 interface.

UTOPIA Level 2 Interface

The UTOPIA Level 2 compliant interface accepts a write clock (TFCLK), a write

enable signal (TENB), the start of a cell (TSOC) indication, and the parity bit

(TPRTY), when data is written to the transmit FIFO (using the rising edges of

TFCLK). The interface provides the transmit cell available status (TCA) which

can transition from "available" to "unavailable" when the transmit FIFO is near full

(when TCALEVEL0 is low) or when the FIFO is full (when TCALEVEL0 is high)

and can accept no more writes. To reduce FIFO latency, the FIFO depth at which

TCA indicates "full" can be set to one, two, three or four cells by the FIFODP[1:0]

bits of the TXCP Configuration 2 register. If the programmed depth is less than

four, more than one cell may be written after TCA is asserted as the TXCP still

allows four cells to be stored in its FIFO.

This interface also indicates FIFO overruns via a maskable interrupt and register

bit, but write accesses while TCA is low are not processed. The TXCP

automatically transmits idle cells until a full cell is available to be transmitted.

UTOPIA Level 3 Interface

The UTOPIA Level 3 compliant interface accepts a write clock (TFCLK), a write

enable signal (TENB), the start of a cell (TSOC) indication and the parity bit

(TPRTY) when data is written to the transmit FIFO (using the rising edges of the

TFCLK). To reduce FIFO latency, the FIFO depth at which TCA indicates “full”

can be set to one, two, three or four cells by the FIFODP[1:0] bits of the TXCP

Configuration 2 register. If the programmed depth is less than four, more than

one cell may be written after TCA is asserted as the TXCP still allows four cells to

be stored in its FIFO.

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