PM5356 datasheet(65/307 Pages) PMC

65 / 307 page

RELEASED

S/UNI-622-MAX

PMC-Sierra, Inc.

PM5356

S/UNI-622-MAX

DATASHEET

PMC-1980589

ISSUE 6

SATURN USER NETWORK INTERFACE (622-MAX)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Figure 6: HCS Verification State Diagram

DETECTION

MODE

ATM DELINEATION

SYNC STATE

CORRECTION

MODE

No Errors Detected

In M Cells

(Pass M Cell)

Apparent Multi-Bit Error

(Drop Cell)

Errors

Detected

(Drop Cell)

No Errors

Detected

(Pass Cell)

ALPHA

consecutive

incorrect HCS's

(To HUNT state)

DELTA

consecutive

correct HCS's

(From PRESYNC

state)

Single-Bit Error

(Correct Error

and Pass Cell)

No Errors Detected

(Pass Cell)

Performance Monitor

The Performance Monitor consists of two 8-bit saturating HCS error event

counters and a 24-bit saturating receive cell counter. The first error counter

accumulates correctable HCS errors, which are HCS single-bit errors, detected

and corrected while the HCS Verification state machine is in the 'Correction

Mode' state. The second error counter accumulates uncorrectable HCS errors,

which are HCS bit errors detected while the HCS Verification state machine is in

the 'Detection Mode' state or HCS bit errors detected but not corrected while the

state machine is in the 'Correction Mode' state. The 24-bit receive cell counter

counts all cells written into the receive FIFO. Filtered cells are not counted.

Each counter may be read through the microprocessor interface. Circuitry is

provided to latch these counters so that their values can be read while

simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a

new period of accumulation can begin without loss of any events. It is intended

that the counter be polled at least once per second so as not to miss any counted

events.

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