PM5356 datasheet(85/307 Pages) PMC

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S/UNI-622-MAX

PMC-Sierra, Inc.

PM5356

S/UNI-622-MAX

DATASHEET

PMC-1980589

ISSUE 6

SATURN USER NETWORK INTERFACE (622-MAX)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Bit

Type

Function

Default

Bit 7

TCLKA

Bit 6

RCLKA

Bit 5

RFCLKA

Bit 4

TFCLKA

Bit 3

Unused

Bit 2

REFCLKA

Bit 1

PICLKA

Bit 0

PTCLKA

This register provides activity monitoring of the S/UNI-622-MAX clocks. When a

monitored clock signal makes a low to high transition, the corresponding register

bit is set high. The bit will remain high until this register is read, at which point all

the bits in this register are cleared. A lack of transitions is indicated by the

corresponding register bit reading low. This register should be read at periodic

intervals to detect clock failures.

PTCLKA:

The PTCLK active (PTCLKA) bit monitors for low to high transition on the

PTCLK parallel transmit clock input. PTCLKA is set high on a rising edge of

PTCLK and is set low when this register is read.

PICLKA:

The PICLK active (PICLKA) bit monitors for low to high transition on the

PICLK parallel receive clock input. PICLKA is set high on a rising edge of

PICLK and is set low when this register is read.

REFCLKA:

The REFCLK active (REFCLKA) bit monitors for low to high transition on the

REFCLK CSU-622 and CRU-622 reference clock input. REFCLKA is set high

on a rising edge of REFCLK and is set low when this register is read.

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