PM5356 datasheet(35/307 Pages) PMC

35 / 307 page

RELEASED

S/UNI-622-MAX

PMC-Sierra, Inc.

PM5356

S/UNI-622-MAX

DATASHEET

PMC-1980589

ISSUE 6

SATURN USER NETWORK INTERFACE (622-MAX)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

TFCLK

Input

M22

UTOPIA transmit FIFO write clock (TFCLK) is used to

write ATM cells to the four cell transmit FIFO.

When in 16-bit Level 2 ATM mode, TFCLK must cycle

at a 50 MHz to 40 MHz instantaneous rate, and must

be a free running clock (cannot be gapped).

When in 8-bit Level 3 ATM mode, TFCLK must cycle

at a 100 MHz to 60 MHz instantaneous rate, and

must be a free running clock (cannot be gapped).

TDAT[0]

TDAT[1]

TDAT[2]

TDAT[3]

TDAT[4]

TDAT[5]

TDAT[6]

TDAT[7]

TDAT[8]

TDAT[9]

TDAT[10]

TDAT[11]

TDAT[12]

TDAT[13]

TDAT[14]

TDAT[15]

Input

K22

K21

K20

J23

J22

J21

H22

H21

H20

G23

G22

G21

G20

F22

F21

E23

The UTOPIA transmit cell data (TDAT[15:0]) bus

carries the ATM cell octets that are written to the

transmit FIFO.

In 16-bit Level 2 ATM mode, the TDAT[15:0] is

considered valid only when TENB is simultaneously

asserted.

In 8-bit Level 3 ATM mode, the TDAT[7:0] bus is

considered valid only when TENB is simultaneously

asserted. TDAT[15:8] are ignored.

TDAT[15:0] is sampled on the rising edge of TFCLK.

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