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PM5356 Datasheet(PDF) 79 Page - PMC-Sierra, Inc |
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PM5356 Datasheet(HTML) 79 Page - PMC-Sierra, Inc |
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79 / 307 page ![]() RELEASED S/UNI-622-MAX PMC-Sierra, Inc. PM5356 S/UNI-622-MAX DATASHEET PMC-1980589 ISSUE 6 SATURN USER NETWORK INTERFACE (622-MAX) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 69 11 NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S/UNI-622-MAX. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[8]) is low. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the S/UNI-622-MAX to determine the programming state of the block. 3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect S/UNI-622-MAX operation unless otherwise noted. Performance monitoring counter registers are a common exception. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-622-MAX operates as intended, reserved register bits must be written with their default value as indicated by the register bit description. 6. Writing any data to the Master Reset and Identity register (0x00) simultaneously loads all the performance monitoring registers in RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP and TXFP blocks in the device. Writing any data to the performance register in question may individually trigger the performance registers in each block. In some cases, all performance registers in the block are loaded. In other cases, only the specific register being written will load. See the register descriptions for the performance register in question for more information. |
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