AD9531 datasheet(35/88 Pages) AD

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Data Sheet

AD9531

cause the PFD frequency to be the active reference frequency,

divided by the value of R1.

Note that, when the ×2 frequency multiplier is in use, the active

reference signal must have a duty cycle close to 50%. Otherwise,

spurious artifacts (or harmonics) may propagate through the

signal path and appear at the output of PLL1.

PLL1 PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMPS

The PFD determines the phase difference between the edges of

the reference divider output and the edges of the feedback divider

output. The maximum operating frequency of the PFD depends

on the operating mode of the PLL (see Table 39).

Table 39. Maximum PFD Rate for PLL1

PLL Mode

Maximum PFD Rate (MHz)

Integer-N

260

Fractional-N

The charge pump circuit provides two pulse-width modulated

output signals: an up pulse and a down pulse. These up/down

pulses drive the charge pump circuit. The instantaneous phase

error determines the amount of charge delivered from the charge

pump to the loop filter. The closed-loop of the PLL tends to drive

the frequency and phase difference between the two PFD input

signals toward zero.

The AD9531 PLL1 contains two separate charge pumps. One is

a 1.8 V charge pump that controls the internal VCO, and the

other is a 3.3 V charge pump that drives an external loop filter

and VCXO (the VCXO is 3.3 V compliant). The 1.8 V charge

pump current is not user-programmable because the PLL1 control

logic automatically sets the 1.8 V charge pump current as required.

The 3.3 V charge pump, however, is user-programmable in

increments of 625 μA up to 5 mA via Register 0x0101, Bits[D4:D2].

PLL1 LOOP FILTER

A loop filter affects the dynamic characteristics (for example, lock

time and stability) of a PLL. When using an external VCXO, a

completely external loop filter is required, as shown in Figure 12.

Conversely, when using the internal VCO, the integrated loop

filter of the AD9531 requires only a single external capacitor or a

series RC combination connected between the LF pin and the

LDOREG1 pin. For a summary of the loop filter component

values, see Table 40.

Table 40. PLL1 Loop Filter Component Values

Component

Loop 1

Loop 2

Loop 2 Wide

Bandwidth

2.75 kΩ

0 Ω

RZ (External)

1 kΩ

Application specific

1 kΩ

CZ (External)

2.7 nF

Application specific

2.7 nF

50 pF

2 kΩ

285 Ω

50 pF

The PLL1 Loop 1 configuration relies on dynamic charge

pump current control to maintain a constant loop bandwidth of

approximately 50 kHz, independent of the value of the N1A feed-

back divider. The Loop 2 and internal Loop 4 configurations,

however, use static charge pump current; therefore, the bandwidth

depends on the feedback divider value.

PLL1 INTERNAL VCO

PLL1 incorporates a low phase noise, LC tank VCO. This VCO has

256 frequency bands spanning from 3500 MHz to 3900 GHz. At

power-up, a VCO calibration cycle begins; this cycle selects the

proper band based on the feedback divider value (see the PLL1

Internal VCO Calibration section).

The internal VCO has an integrated LDO linear voltage regulator

that isolates the VCO from possible external supply voltage

variations. The regulated LDO voltage appears at the

LDOREG1 pin. To ensure stability, connect a 220 nF capacitor

between this pin and ground. This LDO uses anyCAP™ technology

from Analog Devices, Inc., making it insensitive to the type

capacitor used for bypassing purposes.

Note that using the LDOREG1 pin to power an external circuit

may compromise VCO performance.

PLL1 VCO DIVIDER (M1)

The internal VCO operates in the 4 GHz range; this range is too

high to clock the output channel dividers. The purpose of the

M1 divider is to scale down the internal VCO frequency to an

acceptable range for the output channel dividers. The M1 divider is

programmable over a range of 3 to 11.

Under normal operation, there is no need for the user to reset the

M1 divider manually because the VCO calibration process (see the

PLL1 Internal VCO Calibration section) automatically resets M1.

However, when the user wants to change the M1 divider without

recalibrating the PLL1 VCO, the user must execute the following

sequence:

1. Reset the M1 divider (write Register 0x010F, Bits[D3:D0] =

0xF).

2. Issue an input/output update (write Register 0x0005,

Bit D0 = 1).

3. Program the new M1 divider value.

4. Issue an input/output update (write Register 0x0005,

Bit D0 = 1).

PLL1 EXTERNAL VCXO INPUT (RFIN1_x)

The RFIN1_P and RFIN1_N pins are configurable in both

differential and single-ended operation via Register 0x0101,

Bits[D1:D0]. In differential mode, the pins are internally self

biased, and the input signal is ac-coupled via capacitors. In

single-ended mode, only one input is operational, either

RFIN1_P or RFIN1_N, but not both (see Table 57 for details).

Note that the single-ended receivers possess hysteresis and have no

internal bias.

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