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AD9531

Data Sheet

PLL2 VCO DIVIDER (M2)

The internal VCO operates in the 2.4 GHz to 2.5 GHz range;

this range is too high to clock the output channel dividers. The

purpose of the M2 divider is to scale down the VCO frequency to

an acceptable range for the output channel dividers. The M2

divider is program-mable over a range of 3 to 11 via Register

0x0204, Bits[D3:D0].

Under normal operation, there is no need for the user to reset the

M2 divider manually because the VCO calibration process (see

the PLL2 VCO section) automatically resets M2.

However, when the user wants to change the M2 divider without

recalibrating the PLL2 VCO, the user must execute the following

sequence:

1. Reset the M2 divider (write Register 0x0204, Bits[D3:D0] =

0xF).

2. Issue an input/output update (write Register 0x0005,

Bit D0 = 1).

3. Program the new M2 divider value.

4. Issue an input/output update (write Register 0x0005,

Bit D0 =1).

PLL2 FEEDBACK DIVIDER (N2)

The N2 feedback divider is programmable over a useable range

of 13 to 255 via Register 0x0203, Bits[D7:D0]. N2 sets the frequency

multiplication factor from the input of the PFD input to the

output of the VCO.

PLL2 CLOCK DISTRIBUTION

PLL2 Output Groups

The clock distribution section exists as three groups of outputs

(Group 2A, Group 2B, Group 2C, and Group 2D), with each

group having several output drivers that share a channel divider.

Group 2A consists of the D2A channel divider and the output

drivers for OUT2_0 and OUT2_1. Group 2B consists of the D2B

channel divider and the output drivers for OUT2_2 through

OUT2_4. Group 2C consists of the D2C channel divider and the

output drivers for OUT2_5 through OUT2_7. Group 2D consists

of the D2D channel divider and the output drivers for OUT2_8 and

OUT2_11.

PLL2 Channel Dividers

The four channel dividers (D2A, D2B, D2C, and D2D) are

programmable from 0 to 255, corresponding to the divide ratios

of 1 to 256. Note that each channel divider has duty cycle

correction for odd divide ratios.

PLL2 Output Power-Down

The twelve output drivers (OUT2_0 through OUT2_11) have

independent power-down control via the SPI registers. Each

driver has a dedicated power-down bit in its appropriate control

particular driver to Logic 0 powers down the output driver.

Note that powering down all the drivers in a group also powers

down the channel divider associated with that group. For

example, powering down output drivers OUT2_2x through

OUT2_4x automatically powers down D2B as well.

PLL2 Output Mode

The user has independent control of the operating mode of each of

the twelve output channels via the logic mode bits for PLL2 in the

Use HSTL mode and ac-couple the output signal for LVPECL

applications.

Table 44. PLL2 Output Mode Selection

Logic Mode

[2:0]

Description

000

Disable

001

HSTL

010

Undefined

011

Undefined

100

1.8 V CMOS, OUT2_xP active, OUT2_xN active

101

1.8 V CMOS, OUT2_xP active, OUT2_xN disabled

110

1.8 V CMOS, OUT2_xP disabled, OUT2_xN active

111

Undefined

PLL2 Output Polarity

When programming a particular output for 1.8 V CMOS mode,

the polarity of the driver associated with that output is also

programmable (via the polarity bits for PLL2 in the register

map). That is, the logical sense of the output pin, OUT2_xP or

OUT2_xN, is invertible. Table 45 summarizes the polarity options

(normal vs. inverted) for both the positive and negative pins of

the particular 1.8 V CMOS output.

Table 45. Output Polarity, 1.8 V CMOS Mode Only

Polarity, Bits[1:0]

Description

OUT1_xP normal, OUT1_xN inverted

OUT1_xP normal, OUT1_xN normal

OUT1_xP inverted, OUT1_xN inverted

OUT1_xP inverted, OUT1_xN normal

PLL2 Output Clock Divider Synchronization

The sync function allows the user to control the reset of the

channel dividers (D2x) so that they can be phase aligned with

each other. Upon assertion of a sync signal, the sync block holds

the channel dividers reset and disables the clock signals at their

inputs. The clocks driving the channel dividers resume on the

falling edge of the sync signal. Therefore, the sync signal is a

single, positive pulse with both edges necessary to perform

output synchronization.

After the sync block receives a falling edge, it allows the channel

dividers to start up in a known state, even in the absence of an

input clock.

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