AD9531 datasheet(37/88 Pages) AD

37 / 88 page

Data Sheet

AD9531

Note that, if assertion of a sync pulse occurs prior to the PLL

lock and the successful completion of the VCO calibration, then

synchronization of the channel dividers does not occur until

both conditions are satisfied. Otherwise, the channel dividers

synchronize coincident with the falling edge of the sync pulse.

PLL1 HOLDOVER MODE AND FREERUN MODE

PLL1 Holdover Mode

When the AD9531 enters holdover mode, whether invoked

manually or automatically, a reset state is in effect for the PFD

and charge pump (either the 1.8 V or the 3.3 V charge pump,

per the prevailing loop configuration). This mode places the

charge pump in a tristate condition, effectively freezing the state

of charge on the capacitors in the loop filter (either internal or

external per the prevailing loop configuration). By holding the

current state of charge on the loop filter, the VCO control voltage

remains essentially constant, thereby holding the VCO output

frequency at the value it maintained upon entering holdover mode.

Although the VCO frequency remains constant under these

conditions, it is subject to frequency drift caused by charge

injection or bleed off, for example, the capacitor leakage

current or the charge pump leakage current.

PLL1 Freerun Mode

The most important fact regarding freerun mode is that it only

applies to the external loop configurations (Loop 3 or external

Loop 4). When the device enters freerun mode, whether

invoked automatically or manually, it operates much the same

as it does in holdover mode. However, in this case the device

only acts on the 3.3 V charge pump. In addition to the charge

pump entering a tristate condition, an internal resistor connects

the LF pin to an internal voltage equal to half the 3.3 V supply.

The internal resistor, combined with the tristate condition of

the charge pump, effectively holds the VCO control voltage at a

constant 1.65 V.

Manual Holdover Mode/Freerun Mode

Force the device into holdover mode at any time by setting the

holdover bit (Register 0x0102, Bit D6). Note that, if one of the

internal loop configurations is in effect, setting the freerun bit

(Register 0x0102, Bit D7) also forces holdover mode. Be aware,

however, that in this case, the PLL1 freerun bit (Register 0x0082,

Bit D2) is true, even though the device is technically in holdover

mode.

Force the device into freerun mode at any time (assuming an

external loop configuration is in effect) by setting the freerun bit

(Register 0x0102, Bit D7).

Automatic Holdover Mode/Freerun Mode

The AD9531 supports automatic transition to holdover mode

when the enable autohold bit (Register 0x0102, Bit D1) is Logic 1

and the freerun vs. holdover bit (Register 0x0102, Bit D2) is

Logic 0. An automatic transition to holdover happens when the

appropriate LOR states of REF1_A and/or REF1_B occur.

Specifically, if the enable autoswitch bit (Register 0x0102, Bit D0) is

Logic 0, the automatic transition to holdover occurs when the

selected reference (see the Manual Reference Selection section)

indicates LOR (REF1_Ax or REF1_Bx, as the case may be).

However, if the enable auto switch bit is Logic 1, then both

REF1_A and REF1_B must indicate LOR before an automatic

transition to holdover occurs.

Automatic transition to freerun mode occurs in identically the

same manner as an automatic transition to holdover, but only

when an external loop configuration is in effect and both the

enable autohold bit and the freerun vs. holdover bit are both

Logic 1 (Register 0x0102, Bits[D2:D1]).

PLL1 REFERENCE SELECTION—MANUAL AND

AUTOMATIC

Manual Reference Selection

Manual reference selection allows the user to control whether

REF1_A or REF1_B is the active reference. Manual control is

possible via both hardware (the REF1_SEL pin) and software

(by means of the SPI port, Register 0x0102, Bits[D5:D4]).

Hardware-based manual reference selection uses the

REF1_SEL pin to make REF1_A or REF1_B the active

reference. Logic 0 selects REF1_A, whereas Logic 1 selects

REF1_B.

Note that programming the device for automatic reference

switching via the enable autoswitch bit disables the functionality

of the REF1_SEL pin.

Software-based manual reference selection via the SPI port uses the

enable reference select and reference select bits of Register 0x0102.

When the enable reference select bit is Logic 0, manual reference

selection via the SPI port is disabled. When the enable reference

select bit is Logic 1, the reference select bit selects REF1_A or

REF1_B as the active reference: Logic 0 selects REF1_A,

whereas Logic 1 selects REF1_B.

Note that manual reference selection via the SPI port overrides

the automatic reference selection function as well as manual

reference selection via hardware using the REF1_SEL pin.

Automatic Reference Selection

Automatic reference selection allows the device to select a

reference automatically based on the LOR status of PLL1 (see

the Loss of Reference (LOR) section). Automatic reference

selection is in effect when the enable auto switch bit is Logic 1.

Upon LOR indication, the device decides whether to switch

references. If the active reference indicates LOR and the alternate

reference does not, the device automatically switches to the

alternate reference. Otherwise, the currently selected reference

remains the active reference.

When an automatic reference switch occurs, the new reference

becomes the active reference and the other the alternate reference,

which allows the device to switch back and forth between the two

references as required. Be aware, however, that manual reference

selection via Register 0x0102, Bits[D5:D4] overrides this automatic

switching feature.

Rev. 0 | Page 37 of 88

AD9531 Datasheet(PDF) 37 Page - Analog Devices

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