AD9531 datasheet(57/88 Pages) AD

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Data Sheet

AD9531

Registers are generic with normal read/write capability unless

otherwise noted in the option column (Opt.) as follows:

•

A means automatically cleared.

•

B means buffered register (requires an input/output update).

•

R means read only.

•

X means execute ROM load on register write.

•

N/A means not applicable.

The user must avoid writing to register addresses not listed in

Table 52. Such undocumented addresses may have reserved

functionality and writing to them may cause abnormal device

behavior.

Bits labeled unused have no associated physical hardware;

therefore, writing to these bits has no effect.

Bits labelled reserved may have associated hardware. When writing

to reserved bits, use the values in the default column (Def.).

In the default column,

•

Values are hexadecimal, unless otherwise noted.

•

Values with an R prefix indicate that the default values

originate from the ROM and the digits following the R

prefix indicate the ROM indices associated with the

•

The “spec” default value (Register 0x0004) is Logic 0 for all

bits except the D1 bit, which uses ROM default R639 (see

the ROM Profile Data section).

•

The “pin” default value (Register 0x000E) indicates that the

multifunction pins set the default value as described in the

Multifunction Pins (LDET1/M1, LDET2/M2, LDET3/M3,

LOR/M4) section.

Table 52. Register Map

Reg.

Addr.

(Hex)

Opt.

Name

Def.

Serial Port Control Registers

0x0000

N/A

SPI control

Unused

LSB first

Soft reset

Unused

0x00

0x0004

N/A

Serial port

options

Unused

Hardware

reset

Unused

Reduce SPI

strength

Read

buffer

Spec

0x0005

Input/output

(I/O) update

Unused

I/O update

0x00

Device and ROM Profile Identification Registers

0x000A

Device ID

Device ID, Bits[31:24]

0x10

0x000B

Device ID, Bits[23:16]

0x00

0x000C

Device ID, Bits[15:8]

0x08

0x000D

Device ID, Bits[7:0]

0x00

0x000E

Profile

Reserved

ROM profile, Bits[5:0]

Status Registers

0x0080

Status

Reserved

PLL2

calibration

in progress

PLL1

calibration in

progress

Reserved

PLL3 lock

detect

PLL2 lock

detect

PLL1 lock

detect

N/A

0x0081

Unused

REF3 LOR

REF2 LOR

REF1B LOR

REF1A LOR

N/A

0x0082

Unused

Reserved

PLL1 freerun

PLL1

holdover

PLL1 active

reference

N/A

LDET/LOR Control Registers

0x0083

LDET

Reserved

LDET3

3.3 V mode

LDET3

invert

LDET2 3.3 V

mode

LDET2

invert

LDET1 3.3 V

mode

LDET1

invert

ROM

0x0084

LOR

Reserved

3.3 V mode

Invert

REF3 LOR

REF2 LOR

Active REF1

LOR

REF1B LOR

REF1A LOR

ROM

0x0085

LOR2

Reserved

3.3 V mode

Invert

REF3 LOR

REF2 LOR

Active REF1

LOR

REF1B LOR

REF1A LOR

ROM

PLL1 Registers

0x0100

PLL1 General

Registers

Unused

Reserved

Manual

sync

Manual

calibrate

Power-

down

ROM

0x0101

Enable M1

during

VCO

calibration

Fixed delay, Bits[1:0]

3.3 V charge pump current, Bits[2:0]

External oscillator (VCXO)

mode, Bits[1:0]

ROM

0x0102

Freerun

Holdover

Enable

reference

select

Reference

select

Wide

bandwidth

mode

Freerun vs.

holdover

Enable

autohold

Enable

autoswitch

ROM

0x0103

VCO

calibration

reset

REF1B input mode,

Bits[1:0]

REF1B

power-down

Reserved

REF1A input mode, Bits[1:0]

REF1A

power-

down

ROM

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