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AD9531

Data Sheet

LOOP

FILTER

VCO

÷N1B

÷N1A

÷M1

REF1_Ax

REF1_Bx

OUT1_0x

OUT1_9x

REF1_SEL

RFIN1_x

AD9531: PLL1

1.8V

REFERENCE

INPUT

LDOREG1

Figure 14. PLL1 Loop 2 Configuration

LOOP

FILTER

VCO

÷N1A

÷M1

REF1_Ax

REF1_Bx

OUT1_0x

OUT1_9x

REF1_SEL

RFIN1_x

AD9531: PLL1

1.8V

REFERENCE

INPUT

LDOREG1

Figure 15. PLL1 Loop 2 Wide Bandwidth Configuration

PLL1 Loop 2 Configuration (Integrated VCO)

Loop 2 consists of the N1A and N1B dividers in cascade, allowing

lower PFD frequencies than in the Loop 1 configuration. In this

configuration, the charge pump current is constant at 1200 μA

(there is no automatic scaling as in the Loop 1 configuration).

Furthermore, an internal switch shorts RZ in the integrated loop

filter and automatically sets the integrated pole capacitor (CP) to

50 pF. This particular internal loop filter configuration provides

the flexibility to set the response zero and first pole frequency of

the loop filter (via an external RC network) to accommodate a

low PFD rate. Note that Loop 2 configures PLL1 as an integer-N

PLL only.

The VCO frequency is a function of the PFD input frequency (see

the PLL1 Reference Frequency Scaling section) and the values

programmed into the registers associated with N1A and N1B.

fVCO = fPFD × N1A × N1B

where:

N1A is an element of the following set: {15, 16 ... 255}.

N1B is an element of the following set: {4, 5 ... 4095}.

The overall frequency translation equation for Loop 2 is as follows:

N1B

N1A

REF

OUT1

where:

fOUT1 is the frequency at OUT1_x.

fREF is the frequency of the active reference (REF_1A or REF_1B).

R1 is an element of the following set: {½, 1, 4, 5 ... 4,095}. The

value of ½ is the result of selecting the ×2 reference multiplier

(by programming the R1 divider to a value of 0).

OUT1_x and is also an element of the following set: {1, 2 ... 256}.

PLL1 Loop 2 Wide Bandwidth Configuration

To select the Loop 2 wide bandwidth configuration configure

the device for Loop 1 operation per Table 38, but set the wide

bandwidth mode bit (Register 0x0102, Bit D3) to Logic 1.

The Loop 2 wide bandwidth configuration is for applications

requiring improved jitter performance. It is identical to the

standard Loop 2 configuration in most respects. However, there

are two significant differences. First, N1B is not part of the

feedback path. Second, although not shown in Figure 15, the

SDM drives the N1A divider as in the Loop 1 configuration. In

the Loop 2 wide bandwidth configuration however, the SDM

tends to degrade jitter performance significantly. Therefore,

when using the Loop 2 wide bandwidth configuration, it is best

to operate in integer-N mode, which accounts for the exclusion

of the SDM from Figure 15.

The VCO frequency is a function of the PFD input frequency

(see the PLL1 Reference Frequency Scaling section) and the

value programmed into the register associated with N1A.

fVCO = fPFD × N1A

where N1A is an element of the following set: {15, 16 ... 255}.

The overall frequency translation equation for Loop 2 wide

bandwidth is as follows:

N1A

REF

OUT1

where:

fOUT1 is the frequency at OUT1_x.

fREF is the frequency of the active reference (REF_1A or REF_1B).

R1 is an element of the following set: {½, 1, 4, 5 ... 4,095}. The

value of ½ is the result of selecting the ×2 reference multiplier

(by programming the R1 divider to a value of 0).

M1 is an element of the following set: {3, 4 ... 11}.

D1 is the channel divider (D1A, D1B, or D1C) associated with

OUT1_x and is also an element of the following set: {1, 2 ... 256}.

Rev. 0 | Page 32 of 88

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