AD9531 datasheet(38/88 Pages) AD

38 / 88 page

AD9531

Data Sheet

Note that the automatic reference switch feature is nonrevertive.

For example, suppose that REF1_A is the active reference, but

its LOR becomes active, which triggers a reference switch from

REF1_A to REF1_B (assuming REF1_B does not indicate LOR).

This switch makes REF1_B the active reference. Then, suppose

REF1_A subsequently becomes available (meaning its LOR

clears). At this point, instead of the device preferentially reverting to

REF1_A, it retains REF1_B as the active reference until REF1_B

indicates LOR, whereupon a switch back to REF1_A occurs

(assuming REF1_A does not indicate LOR).

PLL1 INTERNAL VCO CALIBRATION

When Loop 1 (integer or fractional-N mode), Loop 2, or the

internal variant of Loop 4 is in effect, the internal VCO is

subject to calibration. Calibration centers the VCO control

voltage at the VCO frequency established after the PLL locks,

allowing the VCO sufficient operating range to maintain lock over

extremes of temperature and voltage (as long as the loop

parameters do not change).

At power-up, the VCO calibration sequence automatically executes,

as long as the multifunction pins select a profile that includes a

VCO calibration command. Otherwise, the user must do so man-

ually via the PLL1 manual calibrate bit (Bit D1 in Register 0x0100).

VCO calibration requires the presence of a reference signal.

Therefore, assuming a signal is present at the REF1_A and/or

REF1_B inputs, the VCO calibration controller awaits indication of

a valid reference signal. Note that, in the absence of a reference

signal, the device remains in VCO calibration mode until a

valid reference is present. Validation of an input signal initiates

the VCO calibration sequence, which allows the loop to lock

and selects the appropriate VCO frequency band.

When the loop parameters change (a new reference frequency

or different feedback divider value, for example), it is necessary

to manually initiate a VCO calibration sequence. To accomplish

this, write the following register sequence:

1. Register 0x0100, Bit D1 = 0 clears the manual calibrate bit.

2. Register 0x0005, Bit D0 = 1 asserts the input/output

update bit.

3. Register 0x0100, Bit D1 = 1 sets the manual calibrate bit.

4. Register 0x0005, Bit D0 = 1 asserts the input/output

update bit.

Note that, when the internal variant of Loop 4 is in effect, VCO

calibration requires special treatment. This is because the M1 and

D1x dividers stop during VCO calibration (a result of the

automatic sync function imposed during calibration), which

prevents the calibration circuitry from receiving the required

feedback clock edges. Therefore, the calibration controller

detects that Loop 4 is in effect and automatically switches to the

Loop 1 configuration to perform the VCO calibration sequence.

Upon completion of the calibration sequence, the calibration

controller automatically restores the Loop 4 configuration.

Note that, because the calibration controller uses the Loop 1

configuration, the N1A divider is necessarily in the feedback

path during the calibration sequence. Therefore, the user must

program the value of the N1A divider before initiating a calibration

sequence in the Loop 4 configuration, such that

N1A = M1 × D1x

That is, N1A must match the product of the M1 divider and the

selected channel divider (D1A, D1B, or D1C, as assigned per the

fixed delay bits of Register 0x0101, Bits[D6:D5]). Programming

N1A to the correct value ensures the calibration controller sets

the correct charge-pump current for the Loop 4 configuration.

Note that, during a VCO calibration sequence, the calibration

controller holds the distribution section in sync mode (channel

dividers reset and output drivers are static) until the calibration

terminates. Therefore, no output signals appear until the VCO

calibration sequence terminates as indicated by a Logic 1 to

Logic 0 transition of the PLL1 calibration in progress bit

(Register 0x0080, Bit D4).

The VCO calibration process requires approximately 172,000 cycles

of the PFD to complete. Therefore, the calibration time (tVCO_CAL)

depends on the input frequency to the PFD as follows:

tVCO_CAL =

PFD

Rev. 0 | Page 38 of 88

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