AD9531 datasheet(6/88 Pages) AD

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AD9531

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Case 4

PLL1: off; PLL3: 3.3 V, CMOS input at 25 MHz, OUT3_0 and OUT3_1 at

125 MHz (1.8 V CMOS and HSTL, respectively); PLL2: off

1.8 V Supply

PLL1 Pins

PLL2 Pins

PLL3 Pins

DVDD Pin

0.3

3.3 V Supply

PLL1 Pins

3.2

PLL2 Pins

1.3

PLL3 Pins

0.1

Case 5

PLL1: differential input at 122.88 MHz, HSTL output at 122.88 MHz, all

outputs active, internal VCO; PLL2: 3.3 V, CMOS input at 50 MHz, HSTL

output at 156.25 MHz, all outputs active; PLL3: 3.3 V, CMOS input at

25 MHz, OUT3_0 and OUT3_1 at 125 MHz (1.8 V CMOS and HSTL,

respectively)

1.8 V Supply

PLL1 Pins

270

PLL2 Pins

280

PLL3 Pins

DVDD Pin

0.3

3.3 V Supply

PLL1 Pins

PLL2 Pins

PLL3 Pins

0.1

INCREMENTAL SUPPLY CURRENT

PLL1, External VCXO Configuration

1.8 V Supply (PLL1 Pins)

−22

3.3 V Supply (PLL1 Pins)

−27

PLL3, Dual Loop Configuration

1.8 V Supply (PLL3 Pins)

3.3 V Supply (PLL3 Pins)

POWER DISSIPATION

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER CONSUMPTION

Does not include power dissipated in the external resistors

Case 1

PLL1: off; PLL2: off; PLL3 off

1.8 V Supply

PLL1 Pins

PLL2 Pins

PLL3 Pins

2.5

DVDD Pin

0.5

3.3 V Supply

PLL1 Pins

PLL2 Pins

4.0

PLL3 Pins

0.3

Rev. 0 | Page 6 of 88

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