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AD9531

Data Sheet

RFIN1_P

RFIN1_N

1.8V

2.5kΩ

0.68V

AD9531

3.3V

TOLERANT

Figure 20. RFIN1_P/RFIN1_N Equivalent Input Circuit

When using an external VCXO with a 3.3 V CMOS single-

ended output, however, it is best to use the differential input

mode to minimize duty cycle distortion. For more information,

see the Interfacing to the RFIN1_x Pins section under

Applications Information.

PLL1 CLOCK DISTRIBUTION

PLL1 Output Groups

The clock distribution section exists as three groups of outputs,

Group 1A, Group 1B, and Group 1C, with each group having

several output drivers that share a channel divider. Group 1A

consists of output drivers for OUT1_0 through OUT1_3 and

the D1A channel divider. Group 1B consists of output drivers

for OUT1_4 through OUT1_7 and the D1B channel divider.

Group 1C consists of output drivers for OUT1_8, OUT1_9, and

the D1C channel divider.

PLL1 Channel Dividers

The three channel dividers—D1A, D1B, and D1C—are program-

mable from a factor of 0 to a factor of 255, corresponding to divide

ratios ranging from 1 to 256. Note that each channel divider has

duty cycle correction for odd divide ratios.

PLL1 Output Power-Down

The ten output drivers (OUT1_0x through OUT1_9x) have

independent power-down control via the SPI registers. Each

driver has a dedicated power-down bit in its appropriate control

particular driver to Logic 0 powers down the output driver.

Note that powering down all the drivers in a group also powers

down the channel divider associated with that group. For

example, powering down output drivers OUT1_4x through

OUT1_7x automatically powers down D1B.

PLL1 Output Operating Mode

The user has independent control of the operating mode of

each of the ten output channels via the logic mode bits for PLL1

in the register map. Table 41 summarizes the operating modes.

For LVPECL applications, use HSTL mode and ac-couple the

output signal.

Table 41. PLL1 Output Mode Selection

Logic Mode,

Bits [2:0]

Description

000

Disable

001

HSTL

010

Undefined

011

Undefined

100

1.8 V CMOS, OUT1_xP active, OUT1_xN active

101

1.8 V CMOS, OUT1_xP active, OUT1_xN disabled

110

1.8 V CMOS, OUT1_xP disabled, OUT1_xN active

111

Undefined

PLL1 Output Polarity

When the user programs a particular output for 1.8 V CMOS

mode, the polarity of the driver associated with that output is

also programmable (via the polarity bits for PLL1 in the register

map). That is, the logical sense of the output pin, OUT1_xP or

OUT1_xN, is invertible. Table 42 summarizes the polarity options

(normal vs. inverted) for both the positive and negative pins of the

particular 1.8 V CMOS output.

Table 42. Output Polarity, 1.8 V CMOS Mode Only

Polarity, Bits[1:0]

Description

OUT1_xP normal, OUT1_xN inverted

OUT1_xP normal, OUT1_xN normal

OUT1_xP inverted, OUT1_xN inverted

OUT1_xP inverted, OUT1_xN normal

PLL1 Output Clock Divider Synchronization (Sync)

The sync function allows the user to control the reset of the

channel dividers (D1x) so that they can be phase aligned with

each other. Upon assertion of a sync signal, the sync block holds

the channel dividers reset and disables the clock signals at their

inputs. The clocks driving the channel dividers resume on the

falling edge of the sync signal. Therefore, the sync signal is a

single, positive pulse with both edges necessary to perform

output synchronization.

After the sync block receives a falling edge, it allows the channel

dividers to start up in a known state, even in the absence of an

input clock.

When using PLL1 in any of the internal VCO operating modes,

the calibration complete and lock detect signals within the control

logic of PLL1 gate the sync function (see the Automatic Output

Synchronization section). Therefore, the output channel dividers

do not synchronize until PLL1 locks, a VCO calibration sequence

executes successfully, and a sync pulse occurs.

Manually force a sync pulse by writing the following register

sequence:

1. Register 0x0100, Bit D2 = 1 to set the manual sync bit.

2. Register 0x0005, Bit D0 = 1 to assert the input/output update

bit.

3. Register 0x0100, Bit D2 = 0 to clear the manual sync bit.

4. Register 0x0005, Bit D0 =1 to assert the input/output update

bit.

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