AD9531 datasheet(34/88 Pages) AD

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AD9531

Data Sheet

LOOP

FILTER

3.3V

VCXO

REF1_Ax

REF1_Bx

OUT1_0x

OUT1_9x

REF1_SEL

RFIN1x

AD9531: PLL1

REFERENCE

INPUT

LDO

REG 1

Figure 18. PLL1 External Loop 4 Configuration

External Loop 4 Configuration

In the external Loop 4 configuration, the feedback divider

consists of one of the channel dividers (D1A, D1B, or D1C).

The particular channel divider included in the feedback path, D1x,

depends on the fixed delay bits (Register 0x0101, Bits[D6:D5]).

Note that M1 is not part of the feedback path in this configuration.

The external configuration uses the 3.3 V charge pump and an

external loop filter and VCXO.

fVCXO = fPFD × D1

where D1 is the channel divider (D1A, D1B, or D1C) associated

with OUT1_x. D1 is also an element of the following set: {1, 2 ...

256}.

The overall frequency translation equation for Loop 4 using an

external VCXO is as follows:

REF

OUT1

where:

fOUT1 is the frequency at OUT1_x.

fREF is the frequency of the active reference (REF_1Ax or

REF_1Bx).

R1 is an element of the following set: {½, 1, 4, 5 ... 4,095}. The

value of ½ is the result of selecting the ×2 reference multiplier

(by programming the R1 divider to a value of 0).

PLL1 REFERENCE CLOCK INPUTS

(REF1_Ax/REF1_Bx)

Two pairs of pins, REF1_Ax and REF1_Bx, provide access to the

reference clock receivers. To accommodate input signals with slow

rising and falling edges, both the differential and single-ended

input receivers use hysteresis. Hysteresis also ensures that a

disconnected or floating input does not cause the receiver to

oscillate.

When configured for differential operation (see Figure 19 and

Table 57), the input receivers accommodate only ac-coupled

input signals. The input receivers are capable of accepting ac-

coupled LVDS and 2.5 V or 3.3 V LVPECL signals. The receiver

is internally dc biased to handle ac-coupled operation. Note that

the receivers do not have an internal resistive termination (50 Ω

or 100 Ω, for example).

REF1_AP

1.8V

REF1_AN

REF1_BP

REF1_BN

1.8V

3.3V

PROGRAMMABLE

2.5V OR 3.3V

LOGIC LEVELS.

3.3V

AD9531

Figure 19. PLL1 Reference Clock Receivers

When configured for single-ended operation (see Figure 19 and

Table 57), the REF1_AP and/or REF1_BP inputs have a user-

programmable input voltage range of 3.3 V or 2.5 V. These pins

possess an internal bias of 1.65 V or 1.25 V (for 3.3 V and 2.5 V

operation, respectively) via an internal resistor of approximately

46 kΩ. This configuration allows either dc coupling (typical) or ac

coupling, with ac coupling preferred for 3.3 V operation. Note that,

when operating in single-ended mode, the REF1_AN and/or

REF1_BN pins are nonfunctional; therefore, connect these pins

directly to ground to avoid parasitic coupling of stray signals.

PLL1 REFERENCE FREQUENCY SCALING

The frequency of the active reference is scalable via the R1 bits

in Register 0x0104 and Register 0x0105 (see Table 58). This

configuration allows the user to scale the reference frequency to

satisfy the input range of the PFD. The frequency appearing at

the input to the PFD of PLL1 depends on the frequency of the

active reference (REF_1A or REF_1B), scaled according to the

following criteria: when R1 = 0, the PFD frequency is twice the

active reference frequency. That is, the ×2 frequency multiplier

is active. A value of 1, 2, or 3 for R1 effectively bypasses the

divider, making the PFD frequency the same as the active

reference frequency. The remaining values of R1 (4 to 4095)

Rev. 0 | Page 34 of 88

AD9531 Datasheet(PDF) 34 Page - Analog Devices

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