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Data Sheet

AD9531

PLL LOCK DETECTION (LDETx)

PLL1, PLL2, and PLL3 each possess a built in digital lock detector

(DLD). PLL1 has a frequency lock detector, whereas PLL2 and

PLL3 have phase lock detectors. Each DLD senses the activity of

its associated PFD to determine if the PLL has acquired a lock

con-dition. The DLDs possess hysteresis to minimize chatter in

the lock detect signal as the loop acquires lock and crosses through

an internal lock/unlock threshold.

The DLDs indicate a logical true state for a lock condition and a

logical false state for an unlock condition. The actual logic level

(Logic 0 or Logic 1) at an LDETx pin depends on the invert bit

for that particular LDET indicator (Register 0x0083, Bit D4,

Bit D2, or Bit D0). When the invert bit is Logic 0, a true DLD

condition appears on an LDETx pin as Logic 1, and a false

condition appears as Logic 0. When the invert bit is Logic 1, a

true DLD condition appears on an LDETx pin as Logic 0, and a

false condition appears as Logic 1.

Furthermore, each of the LDETx pins may be set to 3.3 V logic

(instead of 1.8 V logic) by setting the appropriate 3.3 V mode

bit in Register 0x0083.

AUTOMATIC OUTPUT SYNCHRONIZATION

The output distribution sections associated with PLL1, PLL2,

and PLL3 can have their output channels synchronized so that

all channels of a particular PLL start producing clock signals at

the same instant. The manual sync bit in the register map of a

particular PLL controls the synchronization function for that

particular PLL, as explained in the output synchronization

section of the individual PLL descriptions.

However, output synchronization occurs automatically as the

end result of a reset event, as defined by one of the following

conditions:

•

A POR event

•

A ROM profile load

•

A soft reset (Register 0x0000, Bit D5 = 1)

•

A hardware reset (Register 0x0004, Bit D4 = 1)

Figure 27, Figure 28, and Figure 29 contain flow diagrams

showing the reset sequence for each PLL. Each sequence begins

with a reset event and terminates with the synchronization of

the output channels.

The flowcharts shown in Figure 27, Figure 28, and Figure 29

apply only to a reset event. That is, independent functions included

within the flow of the reset sequence, such as calibrate or sync,

are accessible via the programming registers, even after the reset

sequence terminates. However, when accessed after the termination

of the reset sequence, they behave as independent functions and

do not follow the reset sequence flow.

Figure 27 shows the reset sequence for PLL1. The REF1 pass

and REF1 fail events apply to REF1_A and/or REF1_B, per the

contents of Register 0x0084, Bits[D2:D0]. These bits determine

whether LOR indication is for REF1_A only, REF1_B only, or

the active reference (REF1_A or REF1_B, per the reference

switching controls). Though not explicitly shown in Figure 27, the

flowchart assumes implementation of the features in Figure 21 to

ensure a more robust calibration sequence.

Figure 28 shows the reset sequence for PLL2. The PLL2 flowchart is

similar to the PLL1 flowchart shown in Figure 27, except for the

absence of the external VCXO and fixed delay dependencies.

Though not explicitly shown in Figure 28, the flowchart assumes

implementation of the features in Figure 23 to ensure a more

robust calibration sequence.

Figure 29 shows the reset sequence for PLL3. The PLL3 flowchart is

similar to the PLL2 flowchart shown in Figure 28, except for the

absence of a calibration dependency.

Rev. 0 | Page 51 of 88

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