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Data Sheet

AD9531

TYPICAL PERFORMANCE CHARACTERISTICS

Nominal supply voltage for VDD = 3.3 V and 1.8 V, unless otherwise noted. Jitter integration bandwidth = 12 kHz to 20 MHz.

In the Typical Performance Characteristics section, the following terminology is used: fR is the device input reference clock frequency, fOUT is the

device output clock frequency, LBW is the loop bandwidth of PLLx, and LBW × 2 is the loop bandwidth of PLLx with the ×2 multiplier enabled.

PLL1 CHARACTERISTICS

FREQUENCY OFFSET (Hz)

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–110

–105

–100

–165

100

10k

100k

10M

100M

JITTER: 461fs rms

JITTER BW: 12kHz TO 20MHz

Figure 3. Absolute Phase Noise, fR = 10 MHz, fOUT = 122.88 MHz, 3.3 V CMOS

Single-Ended Input, HSTL Output, Fractional-N PLL Mode, Internal VCO,

LBW = 100 kHz

FREQUENCY OFFSET (Hz)

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–110

–105

–100

–95

100

10k

100k

10M

100M

JITTER: 145fs rms

JITTER BW: 12kHz TO 20MHz

VCXO SPECIFICATION

MANUFACTURER: TAITIEN

P/N: VTEUALJANF-122.88000

Figure 4. Absolute Phase Noise, fR = 10 MHz, fOUT = 122.88 MHz, 3.3 V CMOS

Single-Ended Input, HSTL Output, Integer-N PLL Mode, External VCO,

LBW = 100 Hz

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

–165

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–110

JITTER BW: 12kHz TO 20MHz

fR = 122.88MHz

JITTER: 205fs rms

fR = 245.76MHz

JITTER: 169fs rms

Figure 5. Absolute Phase Noise, fR = 122.88 MHz and 245.76 MHz,

fOUT = 122.88 MHz, Differential Input, HSTL Output, Integer-N PLL Mode,

Internal VCO, Wide Bandwidth Mode, LBW = 300 kHz, LBW × 2 = 565 kHz

Rev. 0 | Page 25 of 88

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