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AD9531

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9531

TOP VIEW

(Not to Scale)

LOR/M4

VDD3_01

NOTES

1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE SOLDERED

TO GROUND TO ACHIEVE THE SPECIFIED THERMAL PERFORMANCE.

OUT3_0

VDD3

REF3_N

REF3_P

VDD3

LDET3/M3

OUT1_9N

OUT1_9P

VDD1_89

OUT1_8N

OUT1_8P

LDET1/M1

OUT1_7N

OUT1_7P

OUT1_6N

OUT1_6P

VDD1_47

OUT1_5N

OUT1_5P

OUT1_4N

OUT1_4P

OUT2_5P

OUT2_5N

OUT2_6P

OUT2_6N

VDD2_57

OUT2_7P

OUT2_7N

OUT2_8P

OUT2_8N

OUT2_9P

OUT2_9N

VDD2_811

OUT2_10P

OUT2_10N

OUT2_11P

OUT2_11N

DVDD_IO

DVDD

SCLK

SDIO

Figure 2. Pin Configuration

Table 37. Pin Function Descriptions

Pin No.

Mnemonic

Supply Domain

Description

LOR/M4

1.8 V/3.3 V

Loss of Reference Pin. This is a multifunction pin.

OUT2_5P

1.8 V

PLL2 Output 5 (Positive).

OUT2_5N

1.8 V

PLL2 Output 5 (Negative).

OUT2_6P

1.8 V

PLL2 Output 6 (Positive).

OUT2_6N

1.8 V

PLL2 Output 6 (Negative).

VDD2_57

1.8 V

PLL2 Power Supply for Channel Outputs OUT2_5 Through OUT2_7.

OUT2_7P

1.8 V

PLL2 Output 7 (Positive).

OUT2_7N

1.8 V

PLL2 Output 7 (Negative).

OUT2_8P

1.8 V

PLL2 Output 8 (Positive).

OUT2_8N

1.8 V

PLL2 Output 8 (Negative).

OUT2_9P

1.8 V

PLL2 Output 9 (Positive).

OUT2_9N

1.8 V

PLL2 Output 9 (Negative).

VDD2_811

1.8 V

PLL2 Power Supply for Channel Outputs OUT2_8 Through OUT2_11.

OUT2_10P

1.8 V

PLL2 Output 10 (Positive).

OUT2_10N

1.8 V

PLL2 Output 10 (Negative).

OUT2_11P

1.8 V

PLL2 Output 11 (Positive).

OUT2_11N

1.8 V

PLL2 Output 11 (Negative).

DVDD_IO

1.8 V/3.3 V

Power Supply for Serial Input/Output Pins.

1.8 V/3.3 V

Chip Select Pin.

DVDD

1.8 V

Power Supply for SPI Registers and PLL1 Digital Σ-Δ Modulator (SDM).

SCLK

1.8 V/3.3 V

Serial Programming Clock.

SDIO

1.8 V/3.3 V

Serial Data Input/Output.

VDD1_3V3

3.3 V

PLL1 REF_A/REF_B Input Receiver Power Supply.

REF1_AP

3.3 V

PLL1 REF_A Input (Positive). Use this pin when operating the REF_A input in single-ended

mode.

Rev. 0 | Page 22 of 88

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