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Data Sheet

AD9531

Address

Bits

Bit Name

Description

0x020F

[D7:D6]

Unused

Unused.

[D5:D3]

Logic mode [2:0]

Configure the OUT2_7x output driver as follows:

000: disabled.

001: HSTL.

010: undefined.

011: undefined.

100: 1.8 V CMOS, OUT2_7P active, OUT2_7N active.

101: 1.8 V CMOS, OUT2_7P active, OUT2_7N disabled.

110: 1.8 V CMOS, OUT2_7P disabled, OUT2_7N active.

111: undefined.

[D2:D1]

Polarity [1:0]

Configure OUT2_7x polarity as follows (applies to CMOS only):

00: OUT2_7P normal, OUT2_7N inverted.

01: OUT2_7P normal, OUT2_7N normal.

10: OUT2_7P inverted, OUT2_7N inverted.

11: OUT2_7P inverted, OUT2_7N normal.

Power-down

0: OUT2_7x driver active.

1: OUT2_7x driver powered down.

Registers for PLL2 Group 2D Outputs, OUT2_8x to OUT2_11x—Register 0x0210 to Register 0x0214

Table 67. PLL2 Group 2D Outputs Register Details

Address

Bits

Bit Name

Description

0x0210

[D7:D0]

D2D [7:0]

D2D divider Bit D7 (MSB) to Bit D0 (LSB). The divide factor is the value of D2D [7:0] + 1. D2D powers

down when all four of the associated output drivers power down, whether via the power-down bit

or via the logic mode bits.

0x0211

[D7:D6]

Unused

Unused.

[D5:D3]

Logic mode [2:0]

Configure the OUT2_8x output driver as follows:

000: disabled.

001: HSTL.

010: undefined.

011: undefined.

100: 1.8 V CMOS, OUT2_8P active, OUT2_8N active.

101: 1.8 V CMOS, OUT2_8P active, OUT2_8N disabled.

110: 1.8 V CMOS, OUT2_8P disabled, OUT2_8N active.

111: undefined.

[D2:D1]

Polarity [1:0]

Configure OUT2_8x polarity as follows (applies to CMOS only):

00: OUT2_8P normal, OUT2_8N inverted.

01: OUT2_8P normal, OUT2_8N normal.

10: OUT2_8P inverted, OUT2_8N inverted.

11: OUT2_8P inverted, OUT2_8N normal.

Power-down

0: OUT2_8x driver active.

1: OUT2_8x driver powered down.

0x0212

[D7:D6]

Unused

Unused.

[D5:D3]

Logic mode [2:0]

Configure OUT2_9 output driver as follows:

000: disabled.

001: HSTL.

010: undefined.

011: undefined.

100: 1.8 V CMOS, OUT2_9P active, OUT2_9N active.

101: 1.8 V CMOS, OUT2_9P active, OUT2_9N disabled.

110: 1.8 V CMOS, OUT2_9P disabled, OUT2_9N active.

111: undefined.

Rev. 0 | Page 73 of 88

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