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Data Sheet

AD9531

feedback dividers (N3A or N3B) to maintain a nearly constant

loop bandwidth of 2 MHz, nominal.

PLL3 LOOP FILTERS

The loop filters associated with PLL3A and PLL3B are identical

and have a third-order response characteristic. The control logic

associated with PLL3A and PLL3B selects the appropriate comp-

onent values of the respective loop filter based on the value of

the respective feedback divider (N3A and N3B). This, in con-

junction with control of the respective charge pump current,

yields a nearly constant loop bandwidth. That is, the closed-

loop bandwidth of PLL3A and PLL3B is a function of the

value of N3A and N3B, respectively, per Table 46.

Table 46. PLL3A/PLL3B Closed-Loop Bandwidth

N3A, N3B1

Nominal Closed-Loop Bandwidth (MHz)

Less than 24

3.5

24 to 47

1.75

Greater than 47

1.0

Table 46 shows that, based on the value of the divider, N3A affects the loop

bandwidth of PLL3A and N3B affects the loop bandwidth of PLL3B.

PLL3 VCOs

The VCOs associated with PLL3A and PLL3B are identical and

have a frequency range of 745 MHz to 805 MHz. Each has a

nominal gain of 750 MHz/V.

PLL3 FEEDBACK DIVIDERS

The feedback dividers associated with PLL3A and PLL3B (N3A

and N3B, respectively) are identical, with divide ranges according

to Register 0x0302 and Register 0x0304 (see Table 69). Program-

ming a value of 0 bypasses the associated PLL. Therefore, when

N3A = 0, the scaled reference input frequency appears at the

input to R3B and when N3B = 0, the output frequency of the R3B

divider appears at the input to the D3A and D3B channel dividers.

PLL3B REFERENCE DIVIDER (R3B)

The R3B reference divider is between PLL3A and PLL3B. R3B

scales the output frequency of the VCO from PLL3A down to a

range suitable for the PFD of PLL3B. The integer factor, R3B, is

variable via Register 0x0303, Bits[D7:D0], per Table 69.

PLL3 CLOCK DISTRIBUTION

Channel Dividers

The two channel dividers (D3A and D3B) are programmable,

providing divide ratios from 1 to 16 (see Table 70 and Table 71

for details). Note that each channel divider has a fixed divide by

2 divider at its output. Therefore, the overall channel divide

ratio is always even and spans a range of 2 to 32.

The channel dividers power down when their associated output

drivers power down.

Output Clock Divider Synchronization

The sync function allows the user to control the reset of the

channel dividers (D3x) so that they can be phase aligned with

each other. Upon assertion of a sync signal, the sync block holds

the channel dividers reset and disables the clock signals at their

inputs. The clocks driving the channel dividers resume on the

falling edge of the sync signal. Therefore, the sync signal is a

single, positive pulse with both edges necessary to perform

output synchronization.

After the sync block receives a falling edge, it allows the channel

dividers to start up in a known state even in the absence of an

input clock.

The sync function is gated by the lock detect signals within the

control logic of PLL3 (see the Automatic Output Synchronization

section). Therefore, the output channel dividers do not synch-

ronize until PLL3A and PLL3B locks and a sync pulse occurs.

The user can manually force a sync pulse by writing the

following register sequence:

1. Register 0x0300, Bit D2 = 1 sets the manual sync bit.

2. Register 0x0005, Bit D0 = 1 asserts the input/output

update bit.

3. Register 0x0300, Bit D2 = 0 clears the manual sync bit.

4. Register 0x0005, Bit D0 = 1 asserts the input/output

update bit.

Note that, if assertion of a sync pulse occurs prior to PLL3 lock,

synchronization of the channel dividers does not occur until the

lock condition is satisfied. Otherwise, the channel dividers

synchronize coincident with the falling edge of the sync pulse.

OUT3_0 Driver

OUT3_0 utilizes a CMOS driver, which normally functions as

an output clock signal for PLL3 and is capable of 1.8 V or 3.3 V

CMOS logic levels as determined by Register 0x0306, Bit D3. In

addition to controlling the output logic levels, the user also has

control over the logical sense of OUT3_0, which is invertible via

independent power-down control via Register 0x0306, Bit D0.

OUT3_0 may function as an optional second LOR pin, as well

(see the Loss of Reference (LOR) section). Note that, when using

OUT3_0 as an LOR pin, Register 0x0306, Bits[D3:D0] are ineff-

ective.

OUT3_1 Driver

OUT3_1 has multiple output driver operating modes, as shown

in Table 47 (see Register 0x0308, Bits[D6:D3]). These modes

include HSTL, LVDS, and 1.8 V or 3.3 V CMOS mode.

For LVPECL applications, use HSTL mode and ac-couple the

output signal.

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