AD9531 datasheet(30/88 Pages) AD

30 / 88 page

AD9531

Data Sheet

THEORY OF OPERATION

The AD9531 includes three independent, fully integrated PLLs

that enable three separate frequency translations (PLL1, PLL2,

and PLL3 in Figure 1). The device has a serial programming

interface (SPI) that allows full control of its many features, as well as

multifunction pins enabling the device to power up in one of 16

possible predefined configurations.

Because PLL1, PLL2, and PLL3 are functionally independent, their

descriptions appear in the following three distinct sections:

•

The PLL1—Integer/Fractional-N PLL section

•

The PLL1 Lock Detector section

•

The PLL3 Integer-N PLL section

PLL1—INTEGER/FRACTIONAL-N PLL

PLL1 is a fractional-N PLL that is also capable of operating in

integer mode (see Figure 12).

PLL1 provides two independent reference clock input signals.

The AD9531 supports differential and single-ended operation

for both reference clocks. PLL1 provides 10 outputs segregated

into three groups. Each group has a dedicated channel divider,

allowing the device to produce three different output frequencies

simultaneously. Note that PLL1 is capable of several different loop

configurations; this data sheet describes each configuration

separately.

PLL1

VCO

PFD

SWITCH

OVER

CONTROL

SDM

REF1_Ax

DLD

HOLDOVER

CONTROL

TRISTATE

CHARGE PUMP

1.8V

CHARGE

PUMP

3.3V

CHARGE

PUMP

LOOP 1

LOOP 2

VDD1_3V3

LDOREG1

LDET1/M1

INTERNAL

LOOP FILTER

RFIN_x

CHARGE

PUMPS

OUT1_0x

÷ N1A

÷ N1B

÷ M1

÷ D1A

÷ D1C

÷ D1B

×2

LOOP FILTER COMPONENT (INTERNAL VCO)

LOOP FILTER COMPONENTS + EXTERNAL VCXO

VCXO

3.3V VCXO

LVCMOS (SINGLE-ENDED)

LVPECL (DIFFERENTIAL)

OUTPUT

REF1_Bx

REF1_SEL

OUT1_1x

OUT1_2x

OUT1_3x

OUT1_4x

OUT1_5x

OUT1_6x

OUT1_7x

OUT1_8x

OUT1_9x

÷ R1

LOOP 3

LOOP 4

3.5GHz TO 3.9GHz

Figure 12. PLL1 Block Diagram

Rev. 0 | Page 30 of 88

AD9531 Datasheet(PDF) 30 Page - Analog Devices

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