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AD9531 Datasheet(PDF) 9 Page - Analog Devices

Part # AD9531
Description  3-Channel Clock Generator, 24 Outputs
PDF  88 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9531 Datasheet(HTML) 9 Page - Analog Devices

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Data Sheet
AD9531
Rev. 0 | Page 9 of 88
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Common-Mode Internally
Generated Bias Voltage
1.0
V
Hysteresis
20
mV
Differential Input Resistance
19
Differential Input Capacitance
3
pF
Duty Cycle
40
60
%
Required for input frequencies below 20 MHz; limited by spurious
performance when ×2 frequency multiplier is in use
CMOS MODE SINGLE-ENDED INPUT
Single-ended operation is only applicable to the REF1_AP and
REF1_BP pins; for both of these inputs, the 2.5 V or 3.3 V mode
is selectable via Register 0x0103
Input Frequency Range
×2 Frequency Multiplier
Bypassed
9.5
260
MHz
Enabled
9.5
100
MHz
Hysteresis
430
mV
Input Resistance
46
Input Capacitance
3
pF
Duty Cycle
40
60
%
Required for input frequencies below 20 MHz; limited by spurious
performance when ×2 frequency multiplier is in use.
3.3 V Operating Mode
Input Voltage
Bias
1.65
V
50% of 3.3 V supply, Pin 23 (VDD1_3V3)
High
2.0
V
Low
1.3
V
2.5 V Operating Mode
Input Voltage
Bias
1.25
V
38% of 3.3 V supply, Pin 23 (VDD1_3V3)
High
1.5
V
Low
0.9
V
PLL1 Distribution Clock Outputs (OUT1_0x to OUT1_9x)
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HSTL MODE
Specifications assume a 100 Ω termination across the
differential output pins
Output Frequency
400
MHz
Rise/Fall Time (20% to 80%)
120
170
ps
Listed values are for the edge (rising or falling) with the
lesser rate of change (|δv/δt|)
Duty Cycle
Up to fOUT = 400 MHz
45
50
55
%
Differential Output Voltage Swing
950
mV
Magnitude of voltage across pins; output driver static
Common-Mode Output Voltage
870
mV
Output driver static
CMOS MODE
Output Frequency
150
MHz
10 pF load
Rise/Fall Time (20% to 80%)
1.0
ns
10 pF load; listed value is for the edge (rising or falling)
with the lesser rate of change (|δv/δt|)
Duty Cycle
50
%
10 pF load
Output Voltage High (VOH)
VDD − 0.2
V
Relative to the VDD1_03, VDD1_47, and VDD1_89 pins,
with the output driver static and IOH = 1 mA
Output Voltage Low (VOL)
0.2
V
Output driver static and IOL = 1 mA



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