 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9531 Datasheet(PDF) 1 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9531 Datasheet(HTML) 1 Page - Analog Devices |
|
|
1 / 88 page  3-Channel Clock Generator, 24 Outputs Data Sheet AD9531 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3) Jitter performance: 0.462 ps rms typical PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth Loss of reference and lock detection for each PLL Pin-configurable common frequency translations Automatic synchronization of all outputs on power-up Manual output synchronization capability Package available in an 88-lead LFCSP PLL1 details Fractional-N/integer-N modes Optional external VCXO Fixed delay mode for constant static phase offset 2 reference clock inputs Input format: differential/single-ended Frequency range: 9.5 MHz to 260 MHz Reference switching: manual/automatic 10 ultralow jitter HSTL/CMOS outputs up to 400 MHz PLL2 details Integer-N mode (1 reference clock input) Input format: differential/single-ended/crystal1 Frequency range: 9.5 MHz to 250 MHz 12 HSTL/CMOS outputs up to 400 MHz PLL3 details Integer-N mode (1 reference clock input) Frequency range: 9.5 MHz to 100 MHz Input format: differential/crystal (supports a 25 MHz to 50 MHz AT-cut quartz crystal resonator) 2 HSTL/LVDS/CMOS outputs to 400 MHz/150 MHz (differential/CMOS) APPLICATIONS Radio equipment controller clocking Low jitter/phase noise clock generation and distribution Clock generation and translation for SONET, 10GE, 10G FC, and other 10 Gbps protocols 40 Gbps/100 Gbps networking line cards, including SONET, synchronous ethernet, OTU2/3/4 Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures Ethernet line cards, switches, and routers SATA and PCI-express GENERAL DESCRIPTION The AD9531 provides a multioutput clock generator function and three on-chip phase-locked loop (PLL) cores with SPI programmable output frequencies and formats. PLL1 provides two reference inputs and 10 outputs and includes four user selectable loop configurations. The PLL has a fully integrated loop filter requiring only a single external capacitor (or a series RC network). PLL1 provides a wide range of output frequencies up to 400 MHz and is capable of operating with an external voltage controlled crystal oscillator (VCXO) and loop filter, instead of the integrated voltage controlled oscillator (VCO) and loop filter. PLL2 is an integer-N PLL providing a single reference input and 12 outputs. PLL2 synthesizes output frequencies up to 400 MHz from the REF2_x source and synchronizes the output clocks to the input reference. PLL3 provides a single reference input and two outputs. PLL3 synthesizes output frequencies up to 400 MHz from the REF3_x source and synchronizes the output clocks to input reference. The AD9531 is available in an 88-lead LFCSP and is specified over the −40°C to +85°C operating temperature range. Throughout this data sheet, multifunction pins, such as LOR/M4, are referred to either by the entire pin name or by a single function of the pin (for example, LOR, when only that function is relevant). In other cases, the text and figures of this data sheet contain references to a channel rather than a pin. For example, REF_A refers to the REF_A channel rather than the REF_AP and REF_AN pins. Likewise, OUT3_1 refers to Channel 1 of PLL3 rather than the OUT3_1P and OUT3_1N pins. Additionally, an abbreviated notation for a pin pair replaces an explicit reference to a each pin (for example, REF_Ax signifies the REF_AN and REF_AP pins.). |
Similar Part No. - AD9531 |
|
Similar Description - AD9531 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
