AD9531 datasheet(63/88 Pages) AD

63 / 88 page

Data Sheet

AD9531

Address

Bits

Bit Name

Description

[D6:D5]

Fixed delay [1:0]

These bits select a particular output distribution group when using the fixed delay function (see

the PLL1 Loop 4 Configuration section).

00: disables the fixed delay function.

01: selects OUT1_0x (Group 1A outputs) as the fixed delay feedback source.

10: selects OUT1_4x (Group 1B outputs) as the fixed delay feedback source.

11: selects OUT1_8x (Group 1C outputs) as the fixed delay feedback source.

[D4:D2]

3.3 V charge pump

current [2:0]

These bits establish the charge pump current for the 3.3 V charge pump of PLL1 (used for

controlling an external VCXO).

000: 625 μA.

001: 1250 μA.

010: 1875 μA.

011: 2500 μA.

100: 3125 μA.

101: 3750 μA.

110: 4375 μA.

111: 5000 μA.

[D1:D0]

External oscillator

(VCXO) mode [1:0]

These bits determine the functionality of the RFIN_1P/RFIN_1N pins when using an external

loop configuration (see the PLL1 Loop Configurations section).

00: disables the external VCXO function.

01: single-ended input (RFIN_1P).

10: single-ended input (RFIN_1N).

11: differential input.

0x0102

Freerun

Logic 1 forces PLL1 into freerun mode, but only if an external loop configuration is in effect.

Otherwise, Logic 1 forces PLL1 into holdover mode.

Holdover

Logic 1 forces PLL1 into holdover mode.

Enable reference

select

0: disables the functionality of the reference select bit.

1: enables the functionality of the reference select bit.

Reference select

This bit is ineffective when Register 0x0102, Bit D5 = 0.

0: forces REF1_A to be the active reference for PLL1.

1: forces REF1_B to be the active reference for PLL1.

Wide bandwidth

mode

See the PLL1 Loop 2 Wide Bandwidth Configuration section for details.

0: disables the wide bandwidth mode.

1: enables the wide bandwidth mode.

Freerun vs.

holdover

Logic 1 allows automatic transition to freerun mode instead of holdover mode. This transition is

only effective when the enable auto hold bit is set and an external loop configuration is in effect.

Enable autohold

Logic 1 activates the control logic that allows automatic transition to holdover mode when

conditions warrant this transition.

Enable autoswitch

Logic 1 activates the control logic that allows automatic switching to an alternate reference

upon LOR indication of the active reference.

0x0103

VCO calibration

reset

0: normal operation (default).

1: resets the PLL1 VCO calibration circuitry. This is a fail-safe control bit. Normally, a reset of the

calibration circuitry automatically occurs at the start of calibration.

[D6:D5]

REF1B input mode

[1:0]

These bits set the configuration of the REF1_B input reference.

00: differential input (REF1_BP/REF1_BN inputs active).

01: 3.3 V CMOS single-ended (REF1_BP active, REF1_BN disabled).

10: not applicable.

11: 2.5 V CMOS single-ended (REF1_BP active, REF1_BN disabled).

REF1B power-down

Logic 1 powers down the REF1_BP/REF1_BN inputs.

Reserved

Reserved.

Rev. 0 | Page 63 of 88

AD9531 Datasheet(PDF) 63 Page - Analog Devices

AD9531 Datasheet(HTML) 63 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL