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AD9531

Data Sheet

PLL3

REF3_N

VDD3

REF3_P

PFD

VCO

720MHz TO

805MHz

VCO

720MHz TO

805MHz

FIXED INTERNAL

LOOP FILTER

RZB

C3B

CPB

CZB

R3B

FIXED INTERNAL

LOOP FILTER

RZA

C3A

CPA

CZA

R3A

CHARGE

PUMP

DLDa

CHARGE

PUMP

DLDb

LDET3/M3

DLDb

OUT3_1x

OUT3_0x

÷ R3A

×2

÷ N3A

÷ D3B

÷ D3A

÷ N3B

DLDb

×2A

÷ R3B

÷ 2

LOR2 MONITOR

PLL3A

PLL3B

×2B

PFD

÷ 2

Figure 24. PLL3 Block Diagram

PLL3 INTEGER-N PLL

PLL3 consists of two, cascaded integer-N PLLs (PLL3A and

PLL3B), each with a loop bandwidth in the range of approximately

2 MHz. A detailed block diagram of PLL3 is shown in Figure 24.

PLL3 REFERENCE CLOCK INPUT (REF3_P/REF3_N)

The differential receiver associated with the REF3_P and

REF3_N pins has a 1.8 V supply. Typically, the user drives the

reference input with a differential signal compatible with 1.8 V

logic levels. For applications with a 3.3 V CMOS reference, see

the Driving REF2 or REF3 with 3.3 V CMOS Logic section in

Applications Information for more details.

The PLL3 reference clock input also supports direct connection to a

crystal resonator. This feature is in effect when the XTAL amplifier

bit (Register 0x0300, Bit D4) is Logic 1. For applications using a

crystal resonator at the reference clock input, see the Using

REF2 or REF3 with a Crystal Resonator section in Applications

Information for more details.

PLL3 INPUT FREQUENCY SCALING

The input frequency applied at REF3 is scalable via R3A per

the user to scale the reference frequency to satisfy the input

range of the PFD. The available frequency scaling factors are as

follows: 2, 1, 2/3, 1/2, 1/3, 1/4, 1/6, and 1/8. Programming

input reference section.

When using the ×2 frequency multiplier in the input reference

section (a frequency scale factor of either 2 or 2/3), the REF3

signal must have a duty cycle close to 50%. Otherwise, spurious

artifacts (harmonics) may propagate through the signal path

and appear at the output of PLL3.

PLL3 PFD AND CHARGE PUMPS

The PFD determines the phase difference between the edges of

the reference divider output and the edges of the feedback

divider output. The circuit provides two pulse-width modulated

output signals: an up pulse and a down pulse. These up/down

pulses drive the charge pump circuit. The instantaneous phase

error determines the amount of charge delivered from the charge

pump to the loop filter. The closed-loop of the PLL tends to drive

the frequency and phase difference between the two PFD input

signals toward 0.

The control logic associated with PLL3A and PLL3B sets the

respective charge pump current based on the value of the

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