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Data Sheet

AD9531

PLL2 Output Timing Skew Matrix (CMOS Mode)

Entries in Table 21 are typical with units of picoseconds (ps) and only apply with a channel divider input frequency less than 650 MHz.

The typical pin load is 10 pF. Any blank cell shown in Table 21 indicates an empty space in the matrix.

Table 21.

OUT2_x1

Group 2A

Group 2B

Group 2C

Group 2D

100

OUT2_x refers to one of the 12 output channels associated with PLL2.

PLL2 Output Isolation, Group to Group

Table 22.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

GROUP TO GROUP ISOLATION

Indicates the worst spur occurring in any channel of the

noninterferer groups; all outputs of all groups active and

configured as HSTL

Group 2A Interferer

Group 2A = 125 MHz, Group 2B = 156.25 MHz, Group 2C =

156.25 MHz, Group 2D = 156.25 MHz

Group 2B Interferer

Group 2A = 156.25 MHz, Group 2B = 125 MHz, Group 2C =

156.25 MHz, Group 2D = 156.25 MHz

Group 2C Interferer

Group 2A = 156.25 MHz, Group 2B = 156.25 MHz, Group 2C =

125 MHz, Group 2D = 156.25 MHz

Group 2D Interferer

Group 2A = 156.25 MHz, Group 2B = 156.25 MHz, Group 2C =

156.25 MHz, Group 2D = 125 MHz

PLL2 VCO and PFD Characteristics

Table 23.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO FREQUENCY RANGE

2400

2500

MHz

An additional 200 ppm margin is allowed beyond these limits

to accommodate input reference drift

PLL FIGURE OF MERIT (FOM)

−222

dBc/Hz

Measured at 500 kHz offset from the output frequency under

the following conditions: fR = 50 MHz, 3.3 V CMOS (single-ended

input), fOUT = 156.25 MHz, (HSTL output)

PFD FREQUENCY RANGE

125

MHz

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