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Data Sheet

AD9531

PLL1 Spurious Performance

Entries in Table 16 indicate the worst spur measured between dc and 1 GHz on any PLL1 output for the given conditions.

Table 16.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SPURIOUS PERFORMANCE

ROM Profile 4

−85

dBc

PLL1: fR = 122.88 MHz, fLOOP = 300 kHz; PLL2: fR = 50 MHz

ROM Profile 5

−85

dBc

PLL1: fR = 10 MHz, fVCXO = 122.88 MHz, fLOOP = 100 Hz; PLL2: fR = 50 MHz

PLL1 Start-Up Time

Table 17.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

START-UP TIME—INTERNAL VCO

Time from application of power (90% of

nominal) to first output clock edge after PLL1

is locked and the outputs are synchronized

fR = 122.88 MHz, fOUT = 122.88 MHz, fPFD = 122.88

MHz, fLOOP = 300 kHz

fR = 10 MHz, fOUT = 122.88 MHz, fPFD = 10 MHz,

fLOOP = 90 kHz, Fractional-N PLL Mode

START-UP TIME—EXTERNAL VCXO

Time from application of power (90% of

nominal) to first output clock edge after PLL1

is locked

fR = 10 MHz, fOUT = 122.88 MHz, fPFD = 80 kHz,

fLOOP = 130 Hz

840

PLL2 CHARACTERISTICS

PLL2 Reference Input (REF2_x)

Table 18.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE CLOCK INPUT PATH

Input Frequency Range

9.5

250

MHz

Input Sensitivity

200

mV p-p

Input Slew Rate

100

V/μs

Minimum limit imposed for jitter performance

Common-Mode Internally Generated

Bias Voltage

1.1

Hysteresis

Differential Input Capacitance

Differential Input Resistance

kΩ

Duty Cycle

Required for input frequencies below 20 MHz when ×2

frequency multiplier is in use

CRYSTAL MOTIONAL RESISTANCE

100

Ω

Use a fundamental mode AT-cut crystal when operating

REF2_x as a crystal resonator input

Rev. 0 | Page 13 of 88

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