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AD9531 Datasheet(PDF) 14 Page - Analog Devices

Part # AD9531
Description  3-Channel Clock Generator, 24 Outputs
PDF  88 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9531 Datasheet(HTML) 14 Page - Analog Devices

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AD9531
Data Sheet
PLL2 Distribution Clock Outputs (OUT2_0x to OUT2_11x)
Table 19.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HSTL MODE
Specifications assume a 100 Ω termination across differential output pins
Output Frequency
400
MHz
Rise/Fall Time (20% to
80%)
120
170
ps
Listed values are for the edge (rising or falling) with the lesser rate of
change (|δv/δt|)
Duty Cycle
Up to fOUT = 400 MHz
45
50
55
%
Differential Output
Voltage Swing
950
mV
Magnitude of voltage across pins; output driver static
Common-Mode Output
Voltage
870
mV
Output driver static
CMOS MODE
Output Frequency
150
MHz
10 pF load
Rise/Fall Time (20% to
80%)
1.0
ns
10 pF load; listed value is for the edge (rising or falling) with the lesser
rate of change (|δv/δt|)
Duty Cycle
50
%
10 pF load
Output Voltage High (VOH)
VDD −
0.2
V
Relative to the VDD2_01, VDD2_24, VDD2_57, and VDD2_811 pins,
with output driver static and IOH = 1 mA
Output Voltage Low (VOL)
0.2
V
Output driver static and IOL = 1 mA
PLL2 Output Timing Skew Matrix (HSTL Mode)
Entries in Table 20 are typical with units of picoseconds (ps) and only apply with a channel divider input frequency less than 650 MHz.
Any blank cell shown in Table 20 indicates an empty space in the matrix.
Table 20.
OUT2_x1
Group 2A
Group 2B
Group 2C
Group 2D
0
1
2
3
4
5
6
7
8
9
10
11
0
20
100
100
100
100
100
100
100
100
100
100
1
100
100
100
100
100
100
100
100
100
100
2
20
20
100
100
100
100
100
100
100
3
20
100
100
100
100
100
100
100
4
100
100
100
100
100
100
100
5
20
20
100
100
100
100
6
20
100
100
100
100
7
100
100
100
100
8
20
20
20
9
20
20
10
20
11
1
OUT2_x refers to one of the 12 output channels associated with PLL2.
Rev. 0 | Page 14 of 88



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