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Data Sheet

AD9531

PLL2

FIXED INTERNAL

LOOP FILTER

VCO

REFERENCE

DETECTOR

DLD

VDD2

LDET2/M2

REF2_N

REF2_P

OUT2_0x

÷ R2

÷ N2

÷ M2

÷ D2A

÷ D2D

÷ D2B

÷ D2C

PFD

CHARGE

PUMP

2.4GHz TO

2.5GHz

OUT2_1x

OUT2_2x

OUT2_3x

OUT2_4x

OUT2_5x

OUT2_6x

OUT2_7x

OUT2_8x

OUT2_9x

OUT2_10x

OUT2_11x

Figure 22. PLL2 Block Diagram

PLL2—INTEGER-N PLL

PLL2 is a fully integrated integer-N PLL that includes a VCO

and internal loop filter (see Figure 22). PLL2 has a single reference

input supporting either a differential clock signal or a crystal

resonator. PLL2 has an output distribution section supporting

twelve outputs segregated into four groups. Each group has a

dedicated channel divider, allowing the device to produce four

different output frequencies simultaneously.

PLL2 reduces the reference input frequency (fREF) via the R2

divider by an integer factor (see the PLL2 Reference Divider

(R2) section), setting the frequency at the input to the PFD.

REF

PFD =

where R2 is an element of the following set: {1, 2 ... 16}.

The PLL core scales the PFD frequency up by an integer

multiple per the feedback divider, N2, yielding the VCO

frequency.

fVCO = fPFD × N2

where N2 is an element of the following set: {20, 21 ... 255}.

The VCO divider, M2, and the channel dividers (D2x) produce

the final output frequency, fOUT2.

VCO

OUT2

where:

fOUT2 is the frequency at OUT2_x.

D2 is the channel divider (D2A, D2B, D2C, or D2D) associated

with OUT2_x.

M2 is an element of the following set: {3, 4 ... 11}.

D2 is an element of the following set: {1, 2 ... 256}.

By substitution, the overall frequency translation is

REF

OUT2

PLL2 REFERENCE CLOCK INPUT (REF2_P/REF2_N)

The differential receiver associated with the REF2_P and

REF2_N pins has a 1.8 V supply. Typically, the user drives the

reference input with a differential signal compatible with 1.8 V

logic levels. For applications with a 3.3 V CMOS reference, see

the Driving REF2 or REF3 with 3.3 V CMOS Logic in the

Applications Information section for more details.

PLL2 REFERENCE DIVIDER (R2)

The function of R2 is to reduce the reference frequency to a

range suitable for the phase detector (125 MHz, maximum). R2

divides by an integer factor ranging from 1 to 16 (see Table 63).

PLL2 PFD AND CHARGE PUMP

The PLL2 PFD determines the phase difference between the

edges of the reference divider output and edges of the feedback

divider output. The circuit provides two pulse-width modulated

output signals: an up pulse and a down pulse. These up/down

pulses drive the charge pump circuit. The instantaneous phase

error determines the amount of charge delivered from the charge

pump to the loop filter. The closed-loop of the PLL tends to drive

the frequency and phase difference between the two PFD input

signals toward 0.

The control logic associated with PLL2 sets the charge pump

current based on the value of the feedback divider, N2, to maintain

a nearly constant loop bandwidth of 500 kHz, nominal.

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