AD9531 datasheet(48/88 Pages) AD

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AD9531

Data Sheet

Table 47. OUT3_1 Output Modes

Logic Mode,

Bits[3:0]

Description

0000

Disabled

0001

HSTL

0010

LVDS

0011

Undefined

0100

1.8 V CMOS, OUT3_1P active, OUT3_1N active

0101

1.8 V CMOS, OUT3_1P active, OUT3_1N disabled

0110

1.8 V CMOS, OUT3_1P disabled, OUT3_1N active

0111 to 1011

Undefined

1100

3.3 V CMOS, OUT3_1P active, OUT3_1N active

1101

3.3 V CMOS, OUT3_1P active, OUT3_1N disabled

1110

3.3 V CMOS, OUT3_1P disabled, OUT3_1N active

1111

Undefined

When the user programs OUT3_1 for 1.8 V or 3.3 V CMOS

mode, the polarity of the driver is also programmable (via the

polarity bits for PLL3 in the register map). That is, the logical

sense of the output pin, OUT3_1P or OUT3_1N, is invertible.

Table 48 summarizes the polarity options (normal vs. inverted).

Table 48. Output Polarity, 1.8 V or 3.3 V CMOS Only

Polarity, Bits[1:0]

Description

OUT3_1P normal, OUT3_1N inverted

OUT3_1P normal, OUT3_1N normal

OUT3_1P inverted, OUT3_1N inverted

OUT3_1P inverted, OUT3_1N normal

Furthermore, the OUT3_1 driver has independent power-down

control via Register 0x0308, Bit D0.

Rev. 0 | Page 48 of 88

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