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Data Sheet

AD9531

PLL3 REGISTERS

PLL3 General Register—Register 0x0300

Table 68. PLL3 General Register Details

Address

Bits

Bit Name

Description

0x0300

[D7:D6]

Unused

Unused.

Reserved

Reserved.

XTAL amplifier

0: configures REF_3P/REF_3N as a differential clock input pair.

1: configures REF_3P/REF_3N as a crystal resonator input. REF_3P/REF_3N is amplifier input/output,

respectively.

Reserved

Reserved.

Manual sync

Write Logic 1 to arm the distribution synchronization circuit, then write Logic 0 to cause the

distribution channel dividers to synchronize (synchronization occurs on the falling edge of this bit).

Reserved

Reserved.

Power-down

Logic 1 causes a full power-down of PLL3.

PLL3 Frequency Translation Registers—Register 0x0301 to Register 0x0304

Table 69. PLL3 Frequency Translation Register Details

Address

Bits

Bit Name

Description

0x0301

[D7:D6]

Unused

Unused.

×2B

Logic 1 enables the ×2 VCO frequency multiplier of PLL3B.

×2A

Logic 1 enables the ×2 VCO frequency multiplier of PLL3A.

[D3:D0]

Reference scaling [3:0]

Reference scaling, Bit D3 (MSB) to Bit D0 (LSB). The value of the reference scaling bits

results in the following behavior:

0: disables reference input section.

1: passes the input frequency unaltered (bypasses R3A).

2: divides the input frequency by 1.5.

3: divides the input frequency by 2.

4: divides the input frequency by 3.

5: divides the input frequency by 4.

6: divides the input frequency by 6.

7: divides the input frequency by 8.

8 to 15: multiplies the input frequency by a factor of 2.

0x0302

[D7:D0]

N3A [7:0]

N3A Bit D7 (MSB) to Bit D0 (LSB). The value of N3A [7:0] results in the following

behavior (avoid values not included in the following ranges):

0: bypasses PLL3A.

8 to 80: divides by this value when ×2A = 0.

15 to 161: divides by this value when ×2A = 1.

0x0303

[D7:D0]

R3B [7:0]

R3B Bit D7 (MSB) to Bit D0 (LSB). The value of R3B [7:0] results in the following

behavior (avoid values not included in the following ranges):

0: bypasses R3B divider.

2 to 10: divides by this value when N3 = 0.

8 to 80: divides by this value when N3 ≠ 0.

0x0304

[D7:D0]

N3B [7:0]

N3B Bit D7 (MSB) to Bit D0 (LSB). The value of N3B [7:0] results in the following

behavior (avoid values not included in the following ranges):

0: bypasses PLL3B.

8 to 80: divides by this value when ×2B = 0.

15 to 161: divides by this value when ×2B = 1.

Rev. 0 | Page 75 of 88

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