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AD9531

Data Sheet

Address

Bits

Bit Name

Description

REF3 LOR

0: disallows loss of reference indication on the LOR/M4 pin by PLL3.

1: allows loss of reference indication on the LOR/M4 pin by PLL3.

REF2 LOR

0: disallows loss of reference indication on the LOR/M4 pin by PLL2.

1: allows loss of reference indication on the LOR/M4 pin by PLL2.

Active REF1 LOR

0: disallows loss of reference indication on the LOR/M4 pin by the active reference of PLL1.

1: allows loss of reference indication on the LOR/M4 pin by the active reference (REF1_A or

REF1_B) of PLL1.

REF1B LOR

0: disallows loss of reference indication on the LOR/M4 pin by REF1_B of PLL1.

1: allows loss of reference indication on the LOR/M4 pin by REF1_B of PLL1.

REF1A LOR

0: disallows loss of reference indication on the LOR/M4 pin by REF1_A of PLL1.

1: allows loss of reference indication on the LOR/M4 pin by REF1_A of PLL1.

0x0085

Reserved

Reserved.

3.3 V mode

This bit controls the output drive voltage of OUT3_0 when any bit of Register 0x0085, Bits[D4:D0] is

Logic 1. In this case, OUT3_0 is a static logic output indicating LOR status per the drive voltage

specified at this bit location (the drive voltage specified by this bit overrides Register 0x0306, Bit D3).

0: OUT3_0 pin = 1.8 V mode LOR indication.

1: OUT3_0 pin = 3.3 V mode LOR indication.

Invert

This bit controls the logical sense of OUT3_0 when any bit of Register 0x0085, Bits[D4:D0] is Logic 1.

In this case, OUT3_0 is a static logic output indicating LOR status with the logical sense specified

at this bit location (the logical sense specified by this bit overrides Register 0x0306, Bit D1).

0: OUT3_0 pin normal (active high logic).

1: OUT3_0 pin inverted (active low logic).

REF3 LOR

0: disallows loss of reference indication on the OUT3_0 pin by PLL3.

1: allows loss of reference indication on the OUT3_0 pin by PLL3.

REF2 LOR

0: disallows loss of reference indication on the OUT3_0 pin by PLL2.

1: allows loss of reference indication on the OUT3_0 pin by PLL2.

Active REF1 LOR

0: disallows loss of reference indication on the OUT3_0 pin by the active reference of PLL1.

1: allows loss of reference indication on the OUT3_0 pin by active reference of PLL1.

REF1B LOR

0: disallows loss of reference indication on the OUT3_0 pin by REF1_B of PLL1.

1: allows loss of reference indication on the OUT3_0 pin by REF1_B of PLL1.

REF1A LOR

0: disallows loss of reference indication on the OUT3_0 pin by REF1_A of PLL1.

1: allows loss of reference indication on the OUT3_0 pin by REF1_A of PLL1.

PLL1 REGISTERS

PLL1 General Registers—Register 0x0100 to Register 0x0103

Table 57. PLL1 General Register Details

Address

Bits

Bit Name

Description

0x0100

[D7:D4]

Unused

Unused.

Reserved

Reserved.

Manual sync

Write Logic 1 to this bit to arm the distribution synchronization circuit, then write Logic 0 to cause the

distribution channel dividers to synchronize (synchronization occurs on the falling edge of this bit).

Manual calibrate

Logic 1 causes the VCO calibration sequence to execute for PLL1. For robustness, write to this bit in

three operations: Logic 0, Logic 1, then Logic 0 with an input/output update following each

operation.

Power-down

Logic 1 causes a full power-down of PLL1.

0x0101

Enable M1 during

VCO calibration

0: normal operation (default). The M1 divider is in a reset state during calibration to ensure a

defined set of initial conditions at power-up or following a device reset.

1: causes the M1 divider to remain active during PLL1 VCO calibration. Allows the user to

observe the calibration process at the clock outputs of PLL1.

Rev. 0 | Page 62 of 88

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