AD9531 datasheet(86/88 Pages) AD

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AD9531

Data Sheet

Figure 44 and Figure 45 demonstrate using the Mx pins with a

1.5 V CMOS logic in a pull-up configuration. A three resistor

arrangement is necessary to satisfy two design criteria as follows:

•

Translate a 1.8 V Logic 1, produced by the internal driver,

to 1.5 V for the external CMOS gate during normal

operation.

•

Provide the desired Logic 1 pull-up to the internal buffer

during a POR event.

The primary design constraint on the pull-up resistor (RU) is

the Logic 0 load current (IL) it imposes on the internal driver

during normal operation. Assuming the external CMOS gate

exhibits high impedance, then RU = 1.8 V/IL. Therefore, choose

a reasonable load current, such as 1 mA, for example. This

yields RU = 1.8 kΩ.

POR

NORM

1.8V

AD9531

1.5V

1.8V

CMOS

Figure 44. Using an Mx Pin with a 1.5 V Logic, Pull-Up Configuration During a

POR Event

1.5V

1.8V

CMOS

POR

NORM

1.8V

AD9531

Figure 45. Using an Mx Pin with a 1.5 V Logic, Pull-Up Configuration During

Normal Operation

In the pull-down case, the series and pull-down resistors must

exhibit a 5:1 ratio to provide the desired 1.8 V to 1.5 V Logic 1

translation between the internal driver and the external CMOS

gate during normal operation. Therefore, the respective R and

5R label for the series and pull-down resistors.

The design goal is to have at least 1.2 V (that is, 2/3 of 1.8 V) on

the Mx pin during a POR event to constitute the desired Logic 1.

RU, R, and 5R form a voltage divider. This divider sets up the

following necessary design constraint:

Because RU = 1.8 V/IL, the above constraint simplifies to R >

0.6/IL and having chosen IL = 1 mA, the result is R > 600 Ω.

Therefore, choose a convenient value such as R = 1 kΩ. This

implies that 5R = 5 kΩ.

INTERFACING TO THE RFIN1_x PINS

Figure 46 is the recommended method for interfacing an

external VCXO with a 3.3 V CMOS single-ended output to the

RFIN1_x pins. Even though the VCXO has a single-ended

output, it is best to configure the RFIN1_x input for differential

input mode to minimize duty cycle distortion. This circuit

works well as long as the stray PCB capacitance (CS) is less than

10 pF and the VCXO frequency is in the range of 120 MHz.

The 0.1 μF capacitor on the RFIN1_N input provides a suitable

ac ground reference for the two 5 pF capacitors, which serve as

a voltage divider for the rising and falling signal edges delivered

by the VCXO output. Typically, the CMOS drivers of most

VCXOs tend to have low output drive capability to minimize

output switching noise and EMI. Therefore, choose small

divider capacitor values to avoid excessive loading of the CMOS

output driver of the VCXO.

RFIN1_P

RFIN1_N

1.8V

2.5kΩ

3.3V

TOLERANT

AD9531

0.1µF

3pF

5pF

VCXO

3.3V

STRAY PCB

CAPACITANCE

5pF

INPUT

CAPACITANCE

MANUFACTURER: TAITIEN

P/N: VTEUALJANF-122.88000

0.68V

Figure 46. Connecting an External 3.3 V CMOS VCXO Single-Ended Output to the RFIN1_x Pins

Rev. 0 | Page 86 of 88

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