AD9531 datasheet(61/88 Pages) AD

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Data Sheet

AD9531

STATUS REGISTERS—REGISTER 0x0080 TO REGISTER 0x0082

Table 55. Status Register Details

Address

Bits

Bit Name

Description

0x0080

[D7:D6]

Reserved

Reserved.

PLL2 calibration

in progress

This bit reflects the state of the PLL2 calibration controller. Logic 1 indicates that the PLL2 internal

VCO calibration is in progress.

PLL1 calibration

in progress

This bit reflects the state of the PLL1 calibration controller. Logic 1 indicates that the PLL1 internal

VCO calibration is in progress.

Reserved

Reserved.

PLL3 lock detect

This bit reflects the state of the lock detector for PLL3. Logic 1 indicates a lock condition for PLL3.

PLL2 lock detect

This bit reflects the state of the lock detector for PLL2. Logic 1 indicates a lock condition for PLL2.

PLL1 lock detect

This bit reflects the state of the lock detector for PLL1. Logic 1 indicates a lock condition for PLL1.

0x0081

[D7:D4]

Unused

Unused.

REF3 LOR

Logic 1 indicates a loss of reference condition for PLL3. Only the first of the two cascaded PLLs of

PLL3 provides the LOR status.

REF2 LOR

Logic 1 indicates a loss of reference condition for PLL2.

REF1B LOR

Logic 1 indicates a loss of reference condition for PLL1 REF1_B.

REF1A LOR

Logic 1 indicates a loss of reference condition for PLL1 REF1_A.

0x0082

[D7:D4]

Unused

Unused.

Reserved

Reserved.

PLL1 freerun

This bit indicates (Logic 1) PLL1 is in freerun mode.

PLL1 holdover

This bit indicates (Logic 1) PLL1 is in holdover mode.

PLL1 active

reference

This bit indicates the currently active reference. Logic 0 indicates REF1_A is the currently active

reference. Logic 1 indicates REF1_B is the currently active reference.

LDET/LOR CONTROL REGISTERS—REGISTER 0x0083 TO REGISTER 0x0085

Register 0x0083 controls the three LDETx pins. Register 0x0084 controls the LOR pin, where Bits[D4:D0] provide logical OR indication

of the various loss of reference detectors at the LOR pin. Register 0x0085 controls the OUT3_0 pin of PLL3, where Bits[D4:D0] provide

logical OR indication of the various loss of referenced detectors on the OUT3_0 pin. When Register 0x0085, Bits[D4:D0] = 00000, the

OUT3_0 pin functions normally (that is, as the output of PLL3).

Table 56. LDETx/LOR Control Register Details

Address

Bits

Bit Name

Description

0x0083

[D7:D6]

Reserved

Reserved.

LDET3 3.3 V mode

0: LDET3/M3 pin, 1.8 V mode.

1: LDET3/M3 pin, 3.3 V mode.

LDET3 invert

0: LDET3/M3 pin normal (active high logic).

1: LDET3/M3 pin inverted (active low logic).

LDET2 3.3 V mode

0: LDET2/M2 pin, 1.8 V mode.

1: LDET2/M2 pin, 3.3 V mode.

LDET2 invert

0: LDET2/M2 pin normal (active high logic).

1: LDET2/M2 pin inverted (active low logic).

LDET1 3.3 V mode

0: LDET1/M1 pin, 1.8 V mode.

1: LDET1/M1 pin, 3.3 V mode.

LDET1 invert

0: LDET1/M1 pin normal (active high logic).

1: LDET1/M1 pin inverted (active low logic).

0x0084

Reserved

Reserved.

3.3 V mode

0: LOR/M4 pin, 1.8 V mode.

1: LOR/M4 pin, 3.3 V mode.

Invert

0: LOR/M4 pin normal (active high logic).

1: LOR/M4 pin inverted (active low logic).

Rev. 0 | Page 61 of 88

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