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Data Sheet

AD9531

APPLICATIONS INFORMATION

INTERFACING TO THE MULTIFUNCTION PINS

Figure 38 and Figure 39 demonstrate using the Mx pins with a

1.8 V CMOS logic. For proper operation during a POR event,

the internal buffer requires a nominal 10 kΩ resistor to pull-up

to 1.8 V (Logic 1) or pull-down to ground (Logic 0). After a

POR event (with S1 in the NORM position), the internal CMOS

driver forces the appropriate 1.8 V logic levels across the 10 kΩ

pull-up or pull-down resistor.

POR

NORM

1.8V

AD9531

1.8V

CMOS

10kΩ

1.8V

Figure 38. Using an Mx Pin with a 1.8 V CMOS Logic, Pull-Up Connection

POR

NORM

1.8V

AD9531

1.8V

CMOS

10kΩ

Figure 39. Using an Mx Pin with a 1.8 V CMOS Logic, Pull-Down Connection

Figure 40 and Figure 41 demonstrate using the Mx pins with a

3.3 V CMOS logic. For proper operation during a POR event,

the internal buffer requires a nominal 10 kΩ resistor to pull-up

to 1.8 V (Logic 1) or pull-down to ground (Logic 0). After a

POR event (normal operation), the internal CMOS driver forces

the appropriate 3.3 V logic levels across the 10 kΩ pull-up or

pull-down resistor. Note that interfacing to 3.3 V CMOS

requires programming the 3.3 V mode bit to Logic 1 for the

associated pin function (LDETx or LOR).

POR

NORM

1.8V

AD9531

3.3V

CMOS

10kΩ

1.8V

3.3V MODE

Figure 40. Using an Mx Pin with a 3.3 V Logic, Pull-Up Configuration

POR

NORM

1.8V

AD9531

3.3V

CMOS

10kΩ

3.3V MODE

Figure 41. Using an Mx Pin with a 3.3 V Logic, Pull-Down Configuration

Figure 42 and Figure 43 demonstrate using the Mx pins with a

1.5 V CMOS logic in a pull-down configuration. A resistive voltage

divider is necessary to properly translate a Logic 1 produced by the

internal driver during normal operation from 1.8 V to 1.5 V.

Therefore, the ratio of the resistors is 5:1. Note the external resistors

have no impact on a Logic 1 produced by the internal driver.

The primary design constraint is the load current (IL) that the

driver must supply for a condition of Logic 1. Assuming the

input of the external CMOS gate exhibits high impedance, then

all the load current flows through the 5R resistor, which must drop

1.5 V. This implies 5R = 1.5 V/IL or R = 0.3 V/IL. Therefore, choose

a reasonable load current, such as 1 mA, for example. This load

current yields R = 300 Ω and 5R = 1.5 kΩ.

During a POR event, the pull-down configuration provides the

internal buffer with a 1.8 kΩ termination to ground, which the

internal buffer interprets as Logic 0. Alternately, during normal

operation, the internal 1.8 V driver delivers a 1.5 V Logic 1 to the

external CMOS gate with 1 mA of load current.

POR

NORM

1.8V

AD9531

1.5V

CMOS

Figure 42. Using an Mx Pin with 1.5 V Logic, Pull-Down Configuration During

a POR Event

POR

NORM

1.8V

AD9531

1.5V

CMOS

Figure 43. Using an Mx Pin with 1.5 V Logic, Pull-Down Configuration During

Normal Operation

Rev. 0 | Page 85 of 88

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