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TMS570LS Datasheet(PDF) 72 Page - Texas Instruments |
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TMS570LS Datasheet(HTML) 72 Page - Texas Instruments |
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72 / 107 page ![]() ECLK 3 4 TMS570LS20206-EP, TMS570LS20216-EP SPNS209A – JUNE 2012 – REVISED AUGUST 2012 www.ti.com 7.2 ECLK Specification 7.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks Table 7-5. Switching Characteristics Over Recommended Operating Conditions For External Clocks(1)(2) NO. Parameter Test Conditions MIN MAX Unit 3 tw(EOL) Pulse duration, ECLK low under all prescale factor 0.5tc(ECLK) – tf ns combinations (X and N) 4 tw(EOH) Pulse duration, ECLK high under all prescale factor 0.5tc(ECLK) – tr ns combinations (X and N) (1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the VBUS interface clock divider ratio determined by the CLKCNTL.[19:16] bits in the SYS module. (2) N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System module. Figure 7-4. ECLK Timing Diagram 72 Peripheral and Electrical Specifications Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP |
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