AD9166 datasheet(101/138 Pages) AD

101 / 138 page

Data Sheet

AD9166

Rev. 0 | Page 101 of 138

Hex.

Addr.

Bit

No.

Bit Name

Settings

Description

Reset

Access

0x31E

PHY_DATA_SNAPSHOT_CTRL

[7:5] Reserved

Reserved.

0x0

[4:2] PHY_GRAB_LANE_SEL

Select from which PHY lane to

grab data.

0x0

R/W

000 Grab data from Lane 0.

001 Grab data from Lane 1.

010 Grab data from Lane 2.

011 Grab data from Lane 3.

100 Grab data from Lane 4.

101 Grab data from Lane 5.

110 Grab data from Lane 6.

111 Grab data from Lane 7.

PHY_GRAB_MODE

Use error trigger to grab data.

0x0

R/W

0 Grab data when

PHY_GRAB_DATA is set.

1 Grab data upon bit error.

PHY_GRAB_DATA

Transition from 0 to 1 causes

logic to store current receive

data from one lane.

0x0

R/W

0x31F

PHY_SNAPSHOT_DATA_BYTE0 [7:0] PHY_SNAPSHOT_DATA_BYTE0

Stores a single byte,

PHY_SNAPSHOT_DATA,

Bits[7:0], of a 40-bit snapshot

(PHY_SNAPSHOT_DATA,

Bits[39:0]) as received on a

single PHY lane. The lane to be

captured and the capture

method is defined in

0x0

0x320

PHY_SNAPSHOT_DATA_

BYTE1

[7:0] PHY_SNAPSHOT_DATA_BYTE1

Stores a single byte,

PHY_SNAPSHOT_DATA,

Bits[15:8], of a 40-bit snapshot

(PHY_SNAPSHOT_DATA,

Bits[39:0]) as received on a

single PHY lane. The lane to be

captured and the capture

method is defined in

0x0

0x321

PHY_SNAPSHOT_DATA_

BYTE2

[7:0] PHY_SNAPSHOT_DATA_BYTE2

Stores a single byte,

PHY_SNAPSHOT_DATA,

Bits[23:16], of a 40-bit

snapshot (PHY_SNAPSHOT_

DATA, Bits[39:0]) as received

on a single PHY lane. The lane

to be captured and the

capture method is defined in

0x0

0x322

PHY_SNAPSHOT_DATA_

BYTE3

[7:0] PHY_SNAPSHOT_DATA_BYTE3

Stores a single byte,

PHY_SNAPSHOT_DATA,

Bits[31:24], of a 40-bit

snapshot (PHY_SNAPSHOT_

DATA, Bits[39:0]) as received

on a single PHY lane. The lane

to be captured and the

capture method is defined in

0x0

0x323

PHY_SNAPSHOT_DATA_

BYTE4

[7:0] PHY_SNAPSHOT_DATA_BYTE4

Stores a single byte,

PHY_SNAPSHOT_DATA,

Bits[39:32], of a 40-bit

snapshot (PHY_SNAPSHOT_

DATA, Bits[39:0]) as received

on a single PHY lane. The lane

to be captured and the

capture method is defined in

0x0

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