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AD9173 Datasheet(PDF) 31 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 31 Page - Analog Devices

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Data Sheet
AD9173
JESD204B SERIAL DATA INTERFACE
analog.com
Rev. C | 31 of 144
Table 15. Single-Link JESD204B Operating Modes
Parameter
Single-Link JESD204B Modes
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
L (Lane Count)
1
2
3
2
4
1
2
1
4
4
4
4
8
8
8
M (Converter Count)
2
4
6
2
4
2
4
4
2
2
2
2
2
2
2
F (Octets per Frame per Lane)
4
4
4
2
2
3
3
8
1
2
1
2
1
2
3
S (Samples per Converter per Frame)
1
1
1
1
1
1
1
1
1
2
1
2
2
4
8
NP (Total Number of Bits per Sample)
16
16
16
16
16
12
12
16
16
16
16
16
16
16
12
N (Converter Resolution)
16
16
16
16
16
12
12
16
16
16
11
11
11
11
11
K (Frames per Multiframe)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
HD (High Density User Data Format)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 16. Dual-Link JESD204B Operating Modes
Parameter
Dual-Link JESD204B Modes
0
1
2
3
4
5
6
7
8
9
13
14
L (Lane Count)
1
2
3
2
4
1
2
1
4
4
4
4
M (Converter Count)
2
4
6
2
4
2
4
4
2
2
2
2
F (Octets per Frame per Lane)
4
4
4
2
2
3
3
8
1
2
1
2
S (Samples per Converter per Frame)
1
1
1
1
1
1
1
1
1
2
1
2
NP (Total Number of Bits per Sample)
16
16
16
16
16
12
12
16
16
16
16
16
N (Converter Resolution)
16
16
16
16
16
12
12
16
16
16
11
11
K (Frames per Multiframe)
32
32
32
32
32
32
32
32
32
32
32
32
HD (High Density User Data Format)
1
1
1
1
1
1
1
1
1
1
1
1
Table 17. Data Structure per Lane for F = 1 JESD204B Operating Modes1
JESD204B Mode and Parameters
Link Logical Lane
Octet 0
Frame 0
Frame 1
L = 4, M = 2, S = 1, NP = 16, N = 16
Mode 8: N = 16
Mode 13: N = 112
Lane 0
M0S0[15:8]
M0S1[15:8]
Lane 1
M0S0[7:0]
M0S1[7:0]
Lane 2
M1S0[15:8]
M1S1[15:8]
Lane 3
M1S0[7:0]
M1S1[7:0]
Mode 15 (L = 8, M = 2, S = 2, NP = 16, N = 112)
Lane 0
M0S0[15:8]
M0S2[15:8]
Lane 1
M0S0[7:0]
M0S2[7:0]
Lane 2
M0S1[15:8]
M0S3[15:8]
Lane 3
M0S1[7:0]
M0S3[7:0]
Lane 4
M1S0[15:8]
M1S2[15:8]
Lane 5
M1S0[7:0]
M1S2[7:0]
Lane 6
M1S1[15:8]
M1S3[15:8]
Lane 7
M1S1[7:0]
M1S3[7:0]
1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.
2 Generate 11-bit resolution data and set Bits[4:0] to 0 for the full 16-bit data packing (NP).



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